Thomas L Cho

US Patent:

6735418, May 11, 2004

Filed:

Mar 16, 2000

Appl. No.:

09/527314

Inventors:

Donald E. MacNally - San Francisco CA
Thomas B. Cho - Alameda CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 144

US Classification:

455 78, 455 80, 455 82

Abstract:

An antenna interface for a Time Division Duplex (TDD) radio transceiver allows a transceiver to be attached to an antenna/filter without the need for an antenna switch. The antenna interface includes a single Balun circuit to convert a single-ended signal to/from differential signals, and a single impedance matching circuit to match an impedance at an output of the single Balun circuit with an input impedance of a Low Noise Amplifier (LNA) of a receiver and to provide an output impedance of a Power Amplifier (PA) of a transmitter. The single impedance matching circuit is coupled to both the LNA and the PA. The LNA and the PA are based on CMOS technology and made within a single integrated circuit.

US Patent:

7065327, Jun 20, 2006

Filed:

Sep 10, 1999

Appl. No.:

09/762720

Inventors:

Donald Evan Macnally - San Francisco CA, US
Thomas B. Cho - Alameda CA, US
Shahriar Rabii - Palo Alto CA, US
Srenik Suresh Mehta - Pleasanton CA, US
Christopher Donald Nilson - San Jose CA, US
Michael Peter Mack - San Francisco CA, US
Laurence Marguerite Plouvier - San Francisco CA, US
Menno Marringa - San Francisco CA, US
Eric S. Dukatz - San Francisco CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 1/44

US Classification:

455 78, 455 83

Abstract:

A single-chip CMOS direct conversion transceiver includes an RF circuit, a transmitter having a synthesizer, a receiver having a baseband filter, and a demodulator. The synthesizer is coupled to the RF circuit. The baseband filter is coupled to the RF circuit and the synthesizer. The demodulator is coupled to the baseband filter. The RF circuit, the synthesizer, the baseband filter, and the demodulator are arranged and configured in CMOS devices and provide a complete interface between an antenna and a voiceband codec.

US Patent:

7283840, Oct 16, 2007

Filed:

Feb 6, 2004

Appl. No.:

10/773609

Inventors:

Thomas Cho - Alameda CA, US

Assignee:

Chrontel, Inc. - San Jose CA

International Classification:

H04M 1/00

US Classification:

4555521, 455 412, 4551272, 4551273, 4551274, 4552451, 4552452, 455339, 455340, 330 98, 330 99, 330100

Abstract:

A dual-mode analog baseband circuit is implementable on a single IC with reduced chip area. The baseband portion of the IC includes a single dual-mode complex filter that is reconfigurable to be a filter for Bluetooth signals or for wireless local area network (wireless LAN) format signals, such as 802. 11b, and includes a single dual-mode amplifier that is reconfigurable to amplify Bluetooth signals or wireless LAN format signals.

US Patent:

20140071721, Mar 13, 2014

Filed:

Nov 12, 2013

Appl. No.:

14/077928

Inventors:

- St. Michael, BB
Shafiq M. Jamal - Gilroy CA, US
Thomas B. Cho - Fremont CA, US
Sehat Sutardja - Los Altos CA, US

Assignee:

Marvell World Trade Ltd. - St Michael

International Classification:

H02M 3/07

US Classification:

363 59

Abstract:

A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage.

US Patent:

61278874, Oct 3, 2000

Filed:

Jul 23, 1998

Appl. No.:

9/121218

Inventors:

Thomas Byunghak Cho - Alameda CA

Assignee:

Level One Communications, Inc. - Sacramento CA

International Classification:

H03F 368
H03F 304

US Classification:

330124R

Abstract:

A low noise amplifier circuit provides high gain and an input impedance matching a source output impedance by combining two amplifiers having different operational characteristics in parallel. The amplifier circuit includes a first amplifier having an input impedance matching a source and a gain less than a system requirement and a second amplifier having a gain meeting the system requirement and an input impedance substantially higher than the input impedance of the first amplifier, the second amplifier being connected in parallel to the first amplifier. The first amplifier includes an input and an output and the second amplifier includes an input and an output, the input to the first amplifier and the input to the second amplifier being connected to the source. A summer is provided for combining an output signal from the first amplifier with an output of the second amplifier. The input impedance of the first amplifier and the input impedance of the second amplifier provide an effective circuit impedance equal to an output impedance of the source.