Thomas Bradley Conte

US Patent:

7865692, Jan 4, 2011

Filed:

Jan 26, 2006

Appl. No.:

11/340072

Inventors:

Sergei Yurievich Larin - Durham NC, US
Gerald George Pechanek - Cary NC, US
Thomas M. Conte - Apex NC, US

Assignee:

Altera Corp. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711217, 711220, 711206, 711125, 711E12058, 711E12002

Abstract:

A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.

US Patent:

7953955, May 31, 2011

Filed:

Dec 14, 2010

Appl. No.:

12/967662

Inventors:

Sergei Yurievich Larin - Durham NC, US
Gerald George Pechanek - Cary NC, US
Thomas M. Conte - Apex NC, US

Assignee:

Altera Corporation. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711217, 711220, 711206, 711125, 711E12058, 711E12002, 712208, 712210, 712300

Abstract:

A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.

US Patent:

20040015931, Jan 22, 2004

Filed:

Apr 10, 2002

Appl. No.:

10/119660

Inventors:

Sergei Larin - Durham NC, US
Gerald Pechanek - Cary NC, US
Thomas Conte - Apex NC, US

Assignee:

BOPS, Inc. - Chapel Hill NC

International Classification:

G06F009/45

US Classification:

717/158000, 717/154000

Abstract:

A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processors using today's technology without posing significant strain on timing requirements.