Thomas M Conte

US Patent:

7865692, Jan 4, 2011

Filed:

Jan 26, 2006

Appl. No.:

11/340072

Inventors:

Sergei Yurievich Larin - Durham NC, US
Gerald George Pechanek - Cary NC, US
Thomas M. Conte - Apex NC, US

Assignee:

Altera Corp. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711217, 711220, 711206, 711125, 711E12058, 711E12002

Abstract:

A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.

US Patent:

7953955, May 31, 2011

Filed:

Dec 14, 2010

Appl. No.:

12/967662

Inventors:

Sergei Yurievich Larin - Durham NC, US
Gerald George Pechanek - Cary NC, US
Thomas M. Conte - Apex NC, US

Assignee:

Altera Corporation. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711217, 711220, 711206, 711125, 711E12058, 711E12002, 712208, 712210, 712300

Abstract:

A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.

US Patent:

8131970, Mar 6, 2012

Filed:

Apr 21, 2009

Appl. No.:

12/427609

Inventors:

Thomas Martin Conte - Atlanta GA, US
Andrew Wolfe - Los Gatos CA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G06F 12/00

US Classification:

711170, 711129, 711130

Abstract:

Techniques a generally described for creating a compiler determined map for the allocation of memory space within a cache. An example computing system is disclosed having a multicore processor with a plurality of processor cores. At least one cache may be accessible to at least two of the plurality of processor cores. A compiler determined map may separately allocate a memory space to threads of execution processed by the processor cores.

US Patent:

8180963, May 15, 2012

Filed:

May 21, 2009

Appl. No.:

12/470256

Inventors:

Thomas Martin Conte - Atlanta GA, US
Andrew Wolfe - Los Gatos CA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G06F 12/00

US Classification:

711117, 711114

Abstract:

The present disclosure relates to a system for hierarchical read-combining memory having a multicore processor operably coupled to a memory controller. The memory controller is configured for receiving a plurality of requests for data from one or more processing cores of the multicore processor, selectively holding a request for data from the plurality of requests for an undetermined or indefinite amount of time, and selectively combining a plurality of requests for the same data into a single read-combined data request. The present disclosure further relates to a method for hierarchical read-combining data requests of a multicore processor and a computer accessible medium having stored thereon computer executable instructions for performing a procedure for hierarchical read-combining data requests of a multicore processor.

US Patent:

8193941, Jun 5, 2012

Filed:

May 6, 2009

Appl. No.:

12/436550

Inventors:

Andrew Wolfe - Los Gatos CA, US
Thomas Martin Conte - Atlanta GA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G08B 23/00
G10K 11/16

US Classification:

340575, 3405731, 381 7111, 381 7114, 381 712

Abstract:

Health-sensing and health-action devices and systems are generally described. The health-sensing device may include one or more of a sensor, a filter, and a transmitter. The sensor may be configured to sense one or more factors relating to an indicator of a health related condition or occurrence such as snoring and may include one or more microphone devices, accelerometers, and/or MEMs devices. The filter may be configured to evaluate a signal from the sensor and determine if the indicator has been detected. The transmitter may be arranged for initiating a transmission based on a signal from the filter. The health-action device may be configured for responding to an indicator of a health related condition or occurrence of a user and may include one or more of a receiver, a processor, and a responder. The health-action device may stimulate the user or may cancel the snoring sound.

US Patent:

8203541, Jun 19, 2012

Filed:

Mar 11, 2009

Appl. No.:

12/402332

Inventors:

Andrew Wolfe - Los Gatos CA, US
Thomas Martin Conte - Atlanta GA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G06F 3/042

US Classification:

345175

Abstract:

The present disclosure relates to a display device with an OLED display including a plurality of nodes configured to emit light when drive circuitry provides a signal across the plurality of nodes at or above an illumination threshold. Measurement circuitry may be disposed proximate to the plurality of nodes and may be configured to sense the light reflected off of an object positioned over the OLED display to provide measurement signals. The measurement signals can be evaluated to determine the location of the display proximate to the object that provides the reflected light.

US Patent:

8243045, Aug 14, 2012

Filed:

Mar 10, 2009

Appl. No.:

12/401124

Inventors:

William Henry Mangione-Smith - Kirkland WA, US
Andrew Wolfe - Los Gatos CA, US
Thomas Martin Conte - Atlanta GA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G06F 3/044

US Classification:

345174

Abstract:

The present disclosure generally relates to a touch-sensitive LED display device with a number of shared circuits having measurement circuitry electrically coupled to display circuitry. A processor receives signals from the measurement circuitry and may compare the signals to determine a location of the touch on the touch screen.

US Patent:

8244982, Aug 14, 2012

Filed:

Aug 21, 2009

Appl. No.:

12/545625

Inventors:

Andrew Wolfe - Los Gatos CA, US
Thomas Martin Conte - Atlanta GA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711128, 711153, 711E12023, 711E12038

Abstract:

Techniques are generally described related to a multi-core processor with a plurality of processor cores and a cache memory shared by at least some of the processor cores. The multi-core processor can be configured for separately allocating a respective level of cache memory associativity to each of the processing cores.

Address:

1689 Colebrook Cir, Decatur, GA 30033

Phone:

4047281228

VIN:

WP0CB298X7U730996

Make:

PORS

Model:

BOXS

Year:

2007