Thomas H George

US Patent:

20210408029, Dec 30, 2021

Filed:

Sep 13, 2021

Appl. No.:

17/473679

Inventors:

- Boise ID, US
Anilkumar Chandolu - Boise ID, US
Indra V. Chary - Boise ID, US
Darwin A. Clampitt - Wilder ID, US
Gordon Haller - Boise ID, US
Thomas George - Boise ID, US
Brett D. Lowe - Boise ID, US
David A. Daycock - Boise ID, US

International Classification:

H01L 27/11573
H01L 21/762
H01L 27/11578
H01L 27/1157
H01L 21/768
H01L 27/11575

Abstract:

A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

US Patent:

20200279867, Sep 3, 2020

Filed:

May 18, 2020

Appl. No.:

16/876896

Inventors:

- Boise ID, US
Anilkumar Chandolu - Boise ID, US
Indra V. Chary - Boise ID, US
Darwin A. Clampitt - Wilder ID, US
Gordon Haller - Boise ID, US
Thomas George - Boise ID, US
Brett D. Lowe - Boise ID, US
David A. Daycock - Boise ID, US

International Classification:

H01L 27/11582
H01L 27/1157
H01L 27/11526
H01L 27/11556
H01L 27/11524
H01L 27/11573

Abstract:

In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

US Patent:

20200119036, Apr 16, 2020

Filed:

Oct 15, 2018

Appl. No.:

16/159955

Inventors:

- Boise ID, US
Anilkumar Chandolu - Boise ID, US
Indra V. Chary - Boise ID, US
Darwin A. Clampitt - Wilder ID, US
Gordon Haller - Boise ID, US
Thomas George - Boise ID, US
Brett D. Lowe - Boise ID, US
David A. Daycock - Boise ID, US

International Classification:

H01L 27/11573
H01L 27/1157
H01L 27/11578
H01L 21/762

Abstract:

A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

US Patent:

20200119040, Apr 16, 2020

Filed:

Oct 15, 2018

Appl. No.:

16/160146

Inventors:

- Boise ID, US
Anilkumar Chandolu - Boise ID, US
Indra V. Chary - Boise ID, US
Darwin A. Clampitt - Wilder ID, US
Gordon Haller - Boise ID, US
Thomas George - Boise ID, US
Brett D. Lowe - Boise ID, US
David A. Daycock - Boise ID, US

International Classification:

H01L 27/11582
H01L 27/1157
H01L 27/11573
H01L 27/11556
H01L 27/11524
H01L 27/11526

Abstract:

In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.