Thomas D Hartnett

US Patent:

6654875, Nov 25, 2003

Filed:

May 17, 2000

Appl. No.:

09/572511

Inventors:

Thomas D. Hartnett - Roseville MN
John S. Kuslak - Blaine MN
Peter B. Criswell - Bethel MN
Wayne D. Ward - New Brighton MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 930

US Classification:

712211, 712200, 712229

Abstract:

Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is compatible with the native instruction set and data words, and the second mode is an adaptation suitable for platform independent instructions. A control word RAM is addressed by the operation code of an instruction, and each word in the control word RAM includes an address into a microcode RAM. The address into the microcode RAM is manipulated in accordance with the various embodiments to reference either a first set of microcode for native instructions and data words, or a second set of microcode for execution in a platform-independent mode.

US Patent:

6751756, Jun 15, 2004

Filed:

Dec 1, 2000

Appl. No.:

09/727610

Inventors:

Thomas D. Hartnett - Roseville MN
John Steven Kuslak - Blaine MN
Douglas A. Fuller - Eagan MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1100

US Classification:

714 54, 714 41, 714 49, 712227

Abstract:

A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also includes programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from a second level cache or storage device.

US Patent:

6839833, Jan 4, 2005

Filed:

Oct 15, 1999

Appl. No.:

09/419439

Inventors:

Thomas D. Hartnett - Roseville MN, US
John S. Kuslak - Blaine MN, US
Leroy J. Longworth - Woodbury MN, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 900

US Classification:

712229, 712 43, 712205

Abstract:

A programmable pipeline depth controller is provided to control the number of instructions that begins execution within an instruction pipeline of an instruction processor within a predetermined period of time. The pipeline depth controller of the present invention includes a logic sequencer responsive to a programmable count value. Upon being enabled, the logic sequencer generates a pipeline control signal to selectively delay the entry of some instructions into the instruction pipeline so that the number of instructions that begins execution within the instruction pipeline during the predetermined period of time following the enabling of the logic sequencer is equal to the count value.

US Patent:

7058793, Jun 6, 2006

Filed:

Dec 20, 1999

Appl. No.:

09/468051

Inventors:

Thomas D. Hartnett - Roseville MN, US
John S. Kuslak - Blaine MN, US
Gary J. Lucas - Pine Springs MN, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 9/40

US Classification:

712219

Abstract:

A synchronous pipeline design is provided that includes a first predetermined number of fetch logic sections, or “stages”, and a second predetermined number of execution stages. Instructions are retrieved from memory and undergo instruction pre-decode and decode operations during the fetch stages of the pipeline. Thereafter, decoded instruction signals are passed to the execution stages of the pipeline, where the signals are dispatched to other execution logic sections to control operand address generation, operand retrieval, any arithmetic processing, and the storing of any generated results. Instructions advance within the various pipeline fetch stages in a manner that may be independent from the way instructions advance within the execution stages. Thus, in certain instances, instruction execution may stall such that the execution stages of the pipeline are not receiving additional instructions to process. This may occur, for example, because an operand required for instruction execution is unavailable.

US Patent:

8301772, Oct 30, 2012

Filed:

Mar 27, 2007

Appl. No.:

11/728617

Inventors:

Michael Zeis - Minneapolis MN, US
Thomas Hartnett - Saint Paul MN, US
Adonijah Park - Forest Lake MN, US

Assignee:

Symantec Corporation - Mountain View CA

International Classification:

G06F 15/16

US Classification:

709226, 709222, 709224

Abstract:

Method and apparatus for allocating resources among backup tasks in a data backup system is described. One aspect of the invention relates to managing backup tasks in a computer network. An estimated resource utilization is established for each of the backup tasks based on a set of backup statistics. A resource reservation is allocated for each of the backup tasks based on the estimated resource utilization thereof. The resource reservation of each of the backup tasks is dynamically changed during performance thereof.

US Patent:

20120209814, Aug 16, 2012

Filed:

Feb 11, 2011

Appl. No.:

13/026188

Inventors:

Xianbo Zhang - Madison WI, US
Thomas Hartnett - Saint Paul MN, US
Weibao Wu - Vadnais Heights MN, US

International Classification:

G06F 17/30

US Classification:

707654, 707E17005

Abstract:

A system and method for caching fingerprints in a client cache is provided. A data object that comprises a set of data segments and describes a backup process is identified. Thereafter, a request referencing the data object is made to a deduplication server to request that a task identifier be added to the data object. If the deduplication server is able to successfully add the task identifier to the data object, then an active identifier is added to each data segment from the set of data segments in a cache that is within a client system.

US Patent:

61674796, Dec 26, 2000

Filed:

Aug 3, 1998

Appl. No.:

9/128297

Inventors:

Thomas D. Hartnett - Roseville MN
John S. Kuslak - Blaine MN
David R. Schroeder - Mounds View MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 948

US Classification:

710260

Abstract:

A system and method is provided for selectively injecting interrupts within the instruction stream of a data processing system. The system includes a programmable storage device for storing interrupt injection signals, each of which is associated with a respective machine instruction. When execution of the associated machine instruction is initiated, the stored signal is read from the storage device and is made available to the interrupt logic within the instruction processor. If set to a predetermined logic level, the signal causes an interrupt to be injected within the instruction processor. The system provides the capability to simultaneously inject different types of interrupts, including fault and non-fault interrupts, during the execution of any instruction. The invention further provides a programmable means for injecting errors at predetermined intervals in the instruction stream. Because the current invention allows interrupt injection to be controlled by programmable logic within the instruction processor itself instead by stimulus generated and controlled by a simulation program as in prior art systems, there is no need to develop complex simulation programs to generate and control the external stimulus.

US Patent:

20150046403, Feb 12, 2015

Filed:

Oct 27, 2014

Appl. No.:

14/524397

Inventors:

- Mountain View CA, US
Thomas Hartnett - Saint Paul MN, US
Weibao Wu - Vadnais Heights MN, US

International Classification:

G06F 11/14

US Classification:

707654

Abstract:

A system and method for caching fingerprints in a client cache is provided. A data object that comprises a set of data segments and describes a backup process is identified. Thereafter, a request referencing the data object is made to a deduplication server to request that a task identifier be added to the data object. If the deduplication server is able to successfully add the task identifier to the data object, then an active identifier is added to each data segment from the set of data segments in a cache that is within a client system.