Thomas P Ho

US Patent:

6744267, Jun 1, 2004

Filed:

Jul 16, 2002

Appl. No.:

10/197134

Inventors:

Frank M. Sauk - San Ramon CA
Gary A. Wells - Fremont CA
Thomas P. Ho - Los Altos CA

Assignee:

NPTest, LLC - San Jose CA

International Classification:

G01R 3102

US Classification:

324754, 324755, 324758

Abstract:

A test system for testing an electronic device is deployable in two basic configurations. In one of the configurations, a load board ( ) that receives a unit ( ) of the device is directly attached to a test head ( ). In the other configuration, the same load board or one having largely the same pattern of test-head signal transmission positions is coupled through an interface apparatus ( ) to a test head. A probe system ( ) contacts that load board or/and the interface apparatus. The interface apparatus is normally configured to largely prevent test-head vibrations from being transferred to the probe system. Additionally or alternatively, the load board is vacuum attached to the interface apparatus.

US Patent:

20070165035, Jul 19, 2007

Filed:

Dec 19, 2006

Appl. No.:

11/613093

Inventors:

Jerome Duluk - Palo Alto CA, US
Richard Hessel - Pleasanton CA, US
Vaughn Arnold - Scotts Valley CA, US
Jack Benkual - Cupertino CA, US
Joseph Bratt - San Jose CA, US
George Cuan - Sunnyvale CA, US
Stephen Dodgen - Boulder Creek CA, US
Emerson Fang - Fremont CA, US
Zhaoyu Gong - Cupertino CA, US
Thomas Ho - Fremont CA, US
Hengwei Hsu - Fremont CA, US
Sidong Li - San Jose CA, US
Sam Ng - Fremont CA, US
Matthew Papakipos - Menlo Park CA, US
Jason Redgrave - Mountain View CA, US
Sushma Trivedi - Sunnyvale CA, US
Nathan Tuck - San Diego CA, US
Shun Go - Milpitas CA, US
Lindy Fung - Sunnyvale CA, US
Tuan Nguyen - San Jose CA, US
Joseph Grass - Menlo Park CA, US
Bo Hung - San Jose CA, US
Abraham Mammen - Pleasanton CA, US
Abbas Rashid - Fremont CA, US
Albert Tsay - Fremont CA, US

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06T 1/20

US Classification:

345506000

Abstract:

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

US Patent:

62688758, Jul 31, 2001

Filed:

Aug 4, 2000

Appl. No.:

9/632293

Inventors:

Jerome F. Duluk - Palo Alto CA
Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
Joseph P. Bratt - San Jose CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Zhaoyu Gong - Cupertino CA
Thomas Y. Ho - Fremont CA
Hengwei Hsu - Fremont CA
Sidong Li - San Jose CA
Sam Ng - Fremont CA
Matthew N. Papakipos - Menlo Park CA
Jason R. Redgrave - Mountain View CA
Sushma S. Trivedi - Sunnyvale CA
Nathan D. Tuck - San Diego CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06T 120

US Classification:

345506

Abstract:

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

US Patent:

62295535, May 8, 2001

Filed:

Aug 20, 1999

Appl. No.:

9/378299

Inventors:

Jerome F. Duluk - Palo Alto CA
Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
Joseph P. Bratt - San Jose CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Zhaoyu Gong - Cupertino CA
Thomas Y. Ho - Fremont CA
Hengwei Hsu - Fremont CA
Sidong Li - San Jose CA
Sam Ng - Fremont CA
Matthew N. Papakipos - Menlo Park CA
Jason R. Redgrave - Mountain View CA
Sushma S. Trivedi - Sunnyvale CA
Nathan D. Tuck - San Diego CA

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

G06T 120

US Classification:

345506

Abstract:

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

US Patent:

47671203, Aug 30, 1988

Filed:

Oct 21, 1987

Appl. No.:

7/111815

Inventors:

Thomas V. Ho - Woodinville WA

International Classification:

A63F 908

US Classification:

273153S

Abstract:

A manually operable mechanical puzzle including four members, each having separable first and second end body portions. Each body portion has an end connector attached to an outer end for pivotal attachment to one of the other members to form a continuous loop comprised of the four members. The first and second body portions of a member are separably attached together at an inner end for partial rotation about an inner end joint. Each of the body portions has a pair of generally oppositely facing attachment faces, each with a square element rotatably attached thereto by a face joint for partial rotation thereabout. When two of said members are pivoted into position laterally adjacent to each other, the first body portions are rotatable as a unit about a common axis formed by the partial inner end joints to selectively interchange attachments of the body portions. In this position, the elements are formed into sets of four elements in a quadrant-like arrangement, with the set being rotatable about a common axis central of the partial face joints to rotate the set of elements to selectively interchange connections with the body portions.