Thomas L Howe

US Patent:

8094641, Jan 10, 2012

Filed:

Aug 19, 2008

Appl. No.:

12/194516

Inventors:

Deepak Mathew - Wilmington MA, US
Russ Mestechkin - Winchester MA, US
Prahallada Ponnathota - Woburn MA, US
Thomas F. Howe - Tyngsboro MA, US
Timothy Perrin Fisher-Jeffes - Cambridge MA, US

Assignee:

MediaTek Inc. - Hsin-Chu

International Classification:

H04B 7/216

US Classification:

370345, 370347

Abstract:

A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.

US Patent:

8391267, Mar 5, 2013

Filed:

Aug 19, 2008

Appl. No.:

12/194521

Inventors:

Prahallada Ponnathota - Woburn MA, US
Thomas F. Howe - Tyngsboro MA, US

Assignee:

MediaTek Inc. - Hsin-chu

International Classification:

H04J 13/00

US Classification:

370342

Abstract:

A wireless system includes a TTI memory architecture in which encoded data are stored in a memory at a rate of one block of encoded data per transmission time interval (TTI), TTI being selected from a set of predetermined values, the memory including memory lines each having a predetermined number of bits that is determined according to the set of predetermined TTI values. For every block of data in which the end of the block of data does not align with an end of a last memory line occupied by the block of data, one or more padded bits are stored after the end of the block of data to the end of the last memory line occupied by the block of data so the last memory line is filled with a portion of the block of data and the one or more padded bits. The block of data and the padded bits are read in one or more equal sized segments.