Thomas J Joyce

US Patent:

50518941, Sep 24, 1991

Filed:

Jan 5, 1989

Appl. No.:

7/294528

Inventors:

Forrest M. Phillips - North Chelmsford MA
Thomas F. Joyce - Westford MA
Ming T. Miu - Chelmsford MA

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 926
G06F 1204

US Classification:

364200

Abstract:

In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alingment of a double word operand that is stored across a double work boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing the non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.

US Patent:

41077741, Aug 15, 1978

Filed:

Oct 4, 1976

Appl. No.:

5/729065

Inventors:

Thomas F. Joyce - Burlington MA
Michel M. Raguin - Medford MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 916

US Classification:

364200

Abstract:

A method and an apparatus for improving the speed of executing instructions and reducing the microprogram memory requirements in a conventional digital computer system. The method or apparatus incorporates the use of a predetermined bit position in the microinstruction word which is set to a binary one when the microword is the last microword of an executing microprogram. The apparatus is responsive to the electronic representation of the binary one signal to cause the microinstruction execution sequence to branch to a predetermined location in the microprogram memory for execution of the following microinstruction; thus, eliminating at least one step in returning to a common address for starting the execution of another microprogram.

US Patent:

42143039, Jul 22, 1980

Filed:

Dec 22, 1977

Appl. No.:

5/863093

Inventors:

Thomas F. Joyce - Burlington MA
Thomas O. Holtey - Newton Lower Falls MA
William Panepinto - Tewksbury MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A word oriented data processing system includes a plurality of system units all connected in common to a system bus. Included are a central processor unit (CPU), a memory system and a high speed buffer or cache system. The cache system is also coupled to the CPU. The cache includes an address directory and a data store with each address location of directory addressing its respective word in data store. The CPU requests a word of cache by sending a memory request to cache which includes a memory address location. If the requested word is stored in the data store, then it is sent to the CPU. If the word is not stored in cache, the cache requests the word of memory. When the cache receives the word from memory, the word is sent to the CPU and also stored in the data store.

US Patent:

43085890, Dec 29, 1981

Filed:

Nov 8, 1979

Appl. No.:

6/093096

Inventors:

Thomas F. Joyce - Burlington MA
Richard A. LeMay - Carlisle MA
William E. Woods - Natick MA
Richard P. Brown - Acton MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 750

US Classification:

364748

Abstract:

The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.

US Patent:

41953410, Mar 25, 1980

Filed:

Dec 22, 1977

Appl. No.:

5/863094

Inventors:

Thomas F. Joyce - Burlington MA
William Panepinto - Tewksbury MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300
G11C 906

US Classification:

364200

Abstract:

A data processing system includes a central processor subsystem, a main memory subsystem and a cache subsystem, all coupled in common to a system bus. During the overall system initialization process, apparatus in the cache subsystem effects the transfer of information from the main memory subsystem to the cache subsystem to load all address locations of the cache subsystem. The transfer of information from the main memory subsystem to the cache subsystem starts from the lowest order address locations in main memory and continues from successive address locations until the cache subsystem is fully loaded. This assures that the cache subsystem contains valid information during normal data processing.

US Patent:

51931818, Mar 9, 1993

Filed:

Oct 5, 1990

Appl. No.:

7/593458

Inventors:

George J. Barlow - Tewksbury MA
James W. Keeley - Nashua NH
Richard A. Lemay - Carlisle MA
Robert V. Ledoux - late of Litchfield NH
Thomas F. Joyce - Westford MA
Richard P. Kelly - Nashua NH
Robert C. Miller - Braintree MA

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1100

US Classification:

395575

Abstract:

The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations.

US Patent:

42952034, Oct 13, 1981

Filed:

Nov 9, 1979

Appl. No.:

6/092907

Inventors:

Thomas F. Joyce - Burlington MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 748

US Classification:

364748

Abstract:

If the firmware calls for an operand rounding operation, apparatus in the Scientific Instruction Processor (SIP) tests the bit to the right of the low order bit of the normalized operand to determine if a rounding cycle is required. If the operand requires a normalization cycle or a mantissa overflow correction cycle, the rounding operation is performed in those cycles.

US Patent:

63112868, Oct 30, 2001

Filed:

Jun 10, 1994

Appl. No.:

8/258752

Inventors:

James F. Bertone - Quincy MA
Bruno DiPlacido - Dedham MA
Thomas F Joyce - Westford MA
Martin Massucci - Burlington MA
Lance J. McNally - Townsend MA
Thomas L. Murray - Hollis NH
Chester M. Nibby - Beverly MA
Michelle A. Pence - Chelmsford MA
Marc Sanfacon - North Chelmsford MA
Jeffrey S. Somers - Lowell MA
G. Lewis Steiner - Milford MA

Assignee:

NEC Corporation - Tokyo

International Classification:

G06F 926

US Classification:

713600

Abstract:

The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.