Thomas E Kazior from Arlington, VA, age 67

Name / Title

Company / Classification

Phones & Addresses

Thomas E Kazior
Director

SYMPHONY PRO MUSICA SOCIETY, INC

PO Box 332, Hudson, MA 01749
34 Blacksmith Dr, Sudbury, MA

Us Patents

Mmic Having Back-Side Multi-Layer Signal Routing
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US Patent:

7387958, Jun 17, 2008
Filed:

Jul 8, 2005
Appl. No.:

11/177732
Inventors:

Christopher P. McCarroll - Andover MA, US
Jerome H. Pozgay - Marblehead MA, US
Steven M. Lardizabal - Westford MA, US
Thomas E. Kazior - Sudbury MA, US
Michael G. Adlerstein - Wellesley MA, US
Assignee:

Raytheon Company - Waltham MA
International Classification:

H01L 21/4763
US Classification:

438622, 438151, 257621, 257758, 257778
Abstract:

A method includes providing a single crystal wafer having MMIC chips. Each chip has an active device in a first surface portion of a semiconductor substrate provided by the wafer and an electrical interconnect having a first portion disposed on a second surface of the semiconductor substrate. The semiconductor substrate structure has a via therethrough, a second portion of the electrical interconnect passing though the via and being electrically connected to the active device. A multilayer interconnect structure is formed on the wafer providing a signal routing section on the second surface portion of a corresponding one of the chips. Each section has dielectric layers and an electrical conductor, such electrical conductor being electrically coupled to the active device to route an electrical signal to such active device. Each chip and the corresponding signal routing section are separated from the wafer.

Passivation Layer For A Circuit Device And Method Of Manufacture
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US Patent:

7767589, Aug 3, 2010
Filed:

Aug 31, 2007
Appl. No.:

11/848820
Inventors:

John M. Bedinger - Garland TX, US
Michael A. Moore - Fort Worth TX, US
Robert B. Hallock - Newton NH, US
Kamal Tabatabaie Alavi - Sharon MA, US
Thomas E. Kazior - Sudbury MA, US
Assignee:

Raytheon Company - Waltham MA
International Classification:

H01L 21/469
H01L 21/31
H01L 23/58
H01L 21/76
US Classification:

438758, 438703, 438761, 438778, 257635, 257632, 257638, 257640, 257E2154
Abstract:

According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0. 01 gram/meter/day, a moisture absorption less than 0. 04 percent, a dielectric constant less than 10, a dielectric loss less than 0. 005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 10ohm-centimeter, and a defect density less than 0. 5/centimeter.

Passivation Layer For A Circuit Device And Method Of Manufacture
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US Patent:

7902083, Mar 8, 2011
Filed:

Jan 21, 2010
Appl. No.:

12/691216
Inventors:

John M. Bedinger - Garland TX, US
Michael A. Moore - Fort Worth TX, US
Robert B. Hallock - Newton NH, US
Kamal Tabatabaie Alavi - Sharon MA, US
Thomas E. Kazior - Sudbury MA, US
Assignee:

Raytheon Company - Waltham MA
International Classification:

H01L 21/469
H01L 21/31
H01L 23/58
H01L 21/76
US Classification:

438758, 438703, 438761, 438778, 257635, 257632, 257638, 257640, 257E2154
Abstract:

According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0. 01 gram/meter/day, a moisture absorption less than 0. 04 percent, a dielectric constant less than 10, a dielectric loss less than 0. 005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 10ohm-centimeter, and a defect density less than 0. 5/centimeter.

Passivation Layer For A Circuit Device And Method Of Manufacture
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US Patent:

RE44303, Jun 18, 2013
Filed:

Aug 2, 2012
Appl. No.:

13/565302
Inventors:

John Bedinger - Garland TX, US
Michael A. Moore - Fort Worth TX, US
Robert B Hallock - Newton NH, US
Kamal Tabatabaie - Sharon MA, US
Thomas E. Kazior - Sudbury MA, US
Assignee:

Raytheon Company - Waltham MA
International Classification:

H01L 21/469
H01L 21/31
H01L 23/58
H01L 21/76
US Classification:

438758, 438703, 438761, 438778, 257635, 257632, 257638, 257640, 257E2154
Abstract:

According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0. 01 gram/meter/day, a moisture absorption less than 0. 04 percent, a dielectric constant less than 10, a dielectric loss less than 0. 005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 10ohm-centimeter, and a defect density less than 0. 5/centimeter.

Gold-Free Ohmic Contacts
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US Patent:

8466555, Jun 18, 2013
Filed:

Jun 3, 2011
Appl. No.:

13/152481
Inventors:

Ram V. Chelakara - Burlington MA, US
Thomas E. Kazior - Sudbury MA, US
Jeffrey R. LaRoche - Lowell MA, US
Assignee:

Raytheon Company - Waltham MA
International Classification:

H01L 23/48
US Classification:

257745, 257382, 257383, 257576, 257624, 257768
Abstract:

A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.

Method And Structure Having Monolithic Heterogeneous Integration Of Compound Semiconductors With Elemental Semiconductor
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US Patent:

8575666, Nov 5, 2013
Filed:

Sep 30, 2011
Appl. No.:

13/249579
Inventors:

Jeffrey R. LaRoche - Lowell MA, US
Thomas E. Kazior - Sudbury MA, US
William E. Hoke - Wayland MA, US
Assignee:

Raytheon Company - Waltham MA
International Classification:

H01L 31/113
US Classification:

257291, 257E29082, 438 34
Abstract:

A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.

Method For Fabricating Semiconductor Devices Having A Substrate Which Includes Group Iii-Nitride Material
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US Patent:

20050258459, Nov 24, 2005
Filed:

May 18, 2004
Appl. No.:

10/848036
Inventors:

Kiuchul Hwang - Amherst NH, US
Thomas Kazior - Sudbury MA, US
International Classification:

H01L029/812
H01L021/338
US Classification:

257280000, 438167000, 438572000, 438604000, 257615000
Abstract:

A method for fabricating a device having a substrate comprising III-N material, such as gallium nitride or aluminum gallium nitride. A surface of the substrate comprising group III-N is oxidized to form an oxide layer comprising III-oxide or III-oxynitride. The layer is formed with a predetermined thickness. Portions of the substrate disposed beneath the upper surface portion remaining un-oxidized. Electrical contacts are formed in ohmic contact without first surface portions of the substrate. An electrical contact is formed in Schottky contact with another surface portion of the substrate after the oxide layer is selectively removed from the upper portion of the substrate.

Monolithic Integrated Circuit Having Enhanced Breakdown Voltage
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US Patent:

20060175631, Aug 10, 2006
Filed:

Feb 4, 2005
Appl. No.:

11/051661
Inventors:

Kiuchul Hwang - Amherst NH, US
Thomas Kazior - Sudbury MA, US
International Classification:

H01L 31/0328
US Classification:

257192000
Abstract:

A field effect transistor structure is provided having: a III-V substrate structure; an InGaAs layer disposed over the substrate structure; an AlGaAs layer disposed on the InGaAs layer; an semiconductor layer disposed on the AlGaAs layer, where the bandgap energy of the semiconductor layer is greater than 1.8 eV; an AlGaAs Schottky layer disposed on the semiconductor layer; and a gate electrode in Schottky contact with the an AlGaAs Schottky layer. In one embodiment, an InGaP or ZnSe layer is disposed on the AlGaAs layer, where the bandgap energy of the InGaP layer is greater than 1.8V and the bandgap energy of the ZnSe layer is greater than 2.6 eV; an AlGaAs Schottky layer disposed on the InGaP layer; and a gate electrode in Schottky contact with the an AlGaAs/InGaP or ZnSe composite Schottky layer.