Thomas Klein

Address:

2710 Chaucer St, Spanish Springs, NV 89436

VIN:

1GCEK19027Z510767

Make:

CHEVROLET

Model:

SILVERADO 1500

Year:

2007

US Patent:

41931831, Mar 18, 1980

Filed:

Jun 26, 1978

Appl. No.:

5/919157

Inventors:

Thomas Klein - Saratoga CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

B01J 1700

US Classification:

29578

Abstract:

A process for constructing self-aligned electrodes overlying a surface of a semiconductor substrate is disclosed. The process utilizes a substrate which is substantially transparent to infrared radiation. One step of the process includes forming spaced apart ones of the electrodes with a conductive material that is highly absorbtive of infrared radiation. Subsequently, a continuous layer of heat sensitive polymer is formed over and between these spaced apart electrodes. The resulting structure is exposed to infrared radiation which heats the spaced apart electrodes. This heat polymerizes the heat sensitive polymer layer in all regions that directly overlie the spaced apart electrodes. These polymerized regions form a mask that is used to construct other electrodes between and in alignment with the spaced apart electrodes.

US Patent:

61785237, Jan 23, 2001

Filed:

Jun 12, 1998

Appl. No.:

9/096696

Inventors:

Thomas Klein - Union City CA

Assignee:

Philips Consumer Communications LP - New York NY

International Classification:

G06F 1100

US Classification:

714 24

Abstract:

A battery-operable portable electronic device, having a removable main power source and an auxiliary power source, generates a power failure interrupt signal when it detects a power failure of the removable main power source. Upon detection of the power failure, the electronic device enters a power down mode in which it monitors recovery from the power failure. The electronic device monitors recovery from the power failure by using a battery check routine it pushes on the stack of a microcontroller, and pops off the battery check routine from the stack upon determining a stable recovery, while returning to an exact point in a main program it left when it detected the power failure, the exact point in the main program being represented by a program counter value automatically pushed on the stack upon occurance of the power failure interrupt signal.

US Patent:

41047842, Aug 8, 1978

Filed:

Apr 1, 1977

Appl. No.:

5/783914

Inventors:

Thomas Klein - Saratoga CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

B01J 1700

US Classification:

29571

Abstract:

A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The process starts with high resistivity material and uses a first ion implant process to dope the field region and to give the required threshold voltage for an enhancement device. A second ion implant is used to dope the channel region for the depletion device.

US Patent:

44751184, Oct 2, 1984

Filed:

Dec 15, 1980

Appl. No.:

6/217425

Inventors:

Thomas Klein - Saratoga CA
Charles E. Boettcher - Sandy UT

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2704
G11C 1140

US Classification:

357 236

Abstract:

An improved dynamic MOS RAM having a plurality of selection lines and data lines and a plurality of storage cells connected thereto, wherein each storage cell includes a storage capacitor having first and second plates, wherein the second plate is adapted to be coupled to a reference potential terminal; and a MOSFET having a semiconductor substrate, a gate connected to one of the selection lines, a first conduction terminal coupled to one of the data lines, and a second conduction terminal connected in common with a first plate of the storage capacitor, is disclosed. The first plate of the storage capacitor includes first doped polysilicon conductive layer that has the majority of its area separated from the semiconductor substrate of the MOSFET by at least an insulating layer. The second plate of the storage capacitor includes a second doped polysilicon conductive layer that is at least coextensive with and insulated from the first conductive layer. The transistor gate is defined by a third doped polysilicon conductive layer that is insulated from the first and second conductive layers.

US Patent:

42901863, Sep 22, 1981

Filed:

Jul 23, 1979

Appl. No.:

6/059637

Inventors:

Thomas Klein - Saratoga CA
Andrew G. Varadi - Saratoga CA
Charles E. Boettcher - Saratoga CA

Assignee:

National Semiconductor Corp. - Santa Clara CA

International Classification:

B01J 1700
H01L 21265

US Classification:

29576B

Abstract:

This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region.

US Patent:

41516311, May 1, 1979

Filed:

May 18, 1977

Appl. No.:

5/798215

Inventors:

Thomas Klein - Saratoga CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

B01J 1700

US Classification:

29571

Abstract:

An IC manufacturing method that eliminates the need for separate pad area and allows polysilicon MOS transistor gates to be contacted directly. Present silicon gate process techniques are utilized up to and including the formation of the gate oxide layer, with areas etched through to the substrate. Then polysilicon and silicon nitride are deposited preferably in the same deposition equipment. The polysilicon interconnect and gate pattern is selectively etched for both silicon nitride and polysilicon. Next, the gate oxide exposed by the previous step is removed and phosphorous is diffused into the exposed silicon substrate surfaces. The initial nitride thickness is chosen such that after phosphorous predeposition and subsequent removal of phosphorous glass, a thin layer of silicon nitride is left. A silicon oxide protective layer is then grown over the exposed silicon substrate surfaces. The remaining silicon nitride is removed and a phosphosilicate glass is deposited over the entire surface.

US Patent:

42053307, May 27, 1980

Filed:

Apr 17, 1978

Appl. No.:

5/896658

Inventors:

Thomas Klein - Saratoga CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2978
H01L 2702

US Classification:

357 23

Abstract:

A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The process starts with high resistivity material and uses a first ion implant process to dope the field region and to give the required threshold voltage for an enhancement device. A second ion implant is used to dope the channel region for the depletion device.

US Patent:

44134010, Nov 8, 1983

Filed:

Jul 6, 1981

Appl. No.:

6/280984

Inventors:

Thomas Klein - Saratoga CA
Andrew G. Varadi - Saratoga CA
Charles E. Boettcher - Saratoga CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

B01J 1700
H01L 21265

US Classification:

29571

Abstract:

This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region.