Thomas A Lane

US Patent:

43618782, Nov 30, 1982

Filed:

Oct 27, 1980

Appl. No.:

6/200876

Inventors:

Thomas A. Lane - New Brighton MN
David M. Webb - Blaine MN

Assignee:

Control Data Corporation - Minneapolis MN

International Classification:

G06F 100

US Classification:

364900

Abstract:

A modified least recently used resolving network provides the capability of ignoring any one or more of the signals indicating use of the device in resolving the least recently used status of the devices.

US Patent:

43909469, Jun 28, 1983

Filed:

Oct 20, 1980

Appl. No.:

6/198888

Inventors:

Thomas A. Lane - New Brighton MN

Assignee:

Control Data Corporation - Minneapolis MN

International Classification:

G06F 922
G06F 928
G06F 938
G06F 942

US Classification:

364200

Abstract:

The microinstructions controlling a pipeline processor are held in a control store that is partitioned into two microcode memory banks. The invention can support three modes of sequencing; single microinstruction, sequential multiple microinstructions, and multiple microinstructions with conditional branching. When a conditional branch is performed, the branch not taken path is assumed and if true, the microinstruction following the branch is executed with no delay. If the branch is taken, the guess is purged and following a one clock delay, the branched to microinstruction is executed. The invention supports these sequencing modes at the maximum pipeline rate, since the only logic between registers is the memory chips.

US Patent:

45119945, Apr 16, 1985

Filed:

Sep 27, 1982

Appl. No.:

6/424665

Inventors:

David M. Webb - Blaine MN
Thomas A. Lane - New Brighton MN

Assignee:

Control Data Corporation - Minneapolis MN

International Classification:

G06F 700
G06F 738

US Classification:

364900

Abstract:

A logic system maintains current least recently used information among the elements of each group in a plurality of groups where each group includes two or more elements. A memory stores intermediate information regarding the relative precedence between each combination of elements in a given group. A logic network recomputes this value each time an element in a group is used and provides this new information to the memory and to a network which resolves the current least recently used status.