Thomas J Magee

US Patent:

20020187595, Dec 12, 2002

Filed:

Oct 30, 2001

Appl. No.:

10/000838

Inventors:

Hans Walitzki - Portland OR, US
Kurt Dichmann - Banks OR, US
Thomas Magee - Lake Oswego OR, US
Claudian Nicolesco - Portland OR, US

Assignee:

Silicon Evolution, Inc. - Vancouver WA

International Classification:

H01L021/338

US Classification:

438/184000

Abstract:

A method for the production of silicon-on-insulator (SOI) wafers for controlling the device layer thickness variations and improvement of bonding quality at the interface of the wafers is disclosed. Using standard etched wafers, a unique sequence of process steps consisting of 2-step front side grinding, free-floating simultaneous double side polishing prepares wafers with low TTV and reduced edge roll off zones. The much smaller unbonded edge zone eliminates the requirements for edge grinding or etching in most cases. When the same s-step grinding/FFS-DSP sequence is applied after bonding and annealing of a Silicon-on-Insulator package, the resulting thickness variation in the device layer is usually smaller than what would be obtained from prior art processes.

US Patent:

20030060020, Mar 27, 2003

Filed:

Oct 11, 2001

Appl. No.:

09/976452

Inventors:

Hans Walitzki - Portland OR, US
Claudian Nicolesco - Portland OR, US
Thomas Magee - Lake Oswego OR, US
Howard Hogle - Portland OR, US

Assignee:

Silicon Evolution, Inc. - Vancouver WA

International Classification:

H01L021/30
H01L021/46
H01L021/302
H01L021/461

US Classification:

438/455000, 438/692000, 438/693000

Abstract:

The present invention relates to the manufacture of substrates for semiconductor device manufacturing particularly for applications that involved wafer-to-wafer bonding for SOI or MEMS structures. Although previous techniques have been applicable to single crystal wafers using bonding and annealing, the current techniques offer the unique capability of utilizing lower cost semiconductor materials, even when they contain dislocations or other growth associated stress fields; such as poly or multi-crystalline silicon and seed, or tail ends of CZ or FZ grown ingots. This invention provides a means of obtaining superior global and local flatness, along with nanoscale roughness variations across the surfaces so that cost and throughput are optimized.