Thomas E Myers

US Patent:

8432237, Apr 30, 2013

Filed:

Aug 14, 2009

Appl. No.:

12/541831

Inventors:

Guy Klemens - San Diego CA, US
Nathan M Pletcher - Encinitas CA, US
Babak Nejati - San Diego CA, US
Norman L Frederick - Vista CA, US
Thomas A Myers - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H01P 5/12
H03H 7/38

US Classification:

333126, 333129, 333132

Abstract:

An output circuit with integrated impedance matching, power combining, and filtering and suitable for use with power amplifiers and other circuits is described. In an exemplary design, an apparatus may include first and second circuits (e. g. , power amplifiers) and an output circuit. The first circuit may provide a first single-ended signal and may have a first output impedance. The second circuit may provide a second single-ended signal and may have a second output impedance. The output circuit may include (i) first and second matching circuits that perform output impedance matching and filtering for the first and second circuits, (ii) a combiner (e. g. , a summing node) that combines the first and second single-ended signals to obtain a combined single-ended signal, (iii) a third matching circuit that performs impedance matching and filtering for the combined single-ended signal, and (iv) switches to route the single-ended signals to different outputs.

US Patent:

8633777, Jan 21, 2014

Filed:

Dec 1, 2009

Appl. No.:

12/628502

Inventors:

Zhang Jin - San Diego CA, US
Aristotele Hadjichristos - San Diego CA, US
Hongyan Yan - San Diego CA, US
Guy Klemens - San Diego CA, US
Maulin P. Bhagat - San Diego CA, US
Thomas Myers - San Diego CA, US
Norman L. Frederick - San Diego CA, US
Junxiong Deng - San Diego CA, US
Aleksandar Tasic - San Diego CA, US
Bhushan S. Asuri - San Diego CA, US
Mohammad Farazian - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03B 1/00

US Classification:

331167, 331117 R, 331117 FE

Abstract:

An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits.

US Patent:

20100327976, Dec 30, 2010

Filed:

Feb 12, 2010

Appl. No.:

12/705493

Inventors:

Guy Klemens - San Diego CA, US
Thomas A. Myers - San Diego CA, US
Yu Zhao - San Diego CA, US
Babak Nejati - San Diego CA, US
Nathan M. Pletcher - Encinitas CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03F 3/16

US Classification:

330277

Abstract:

A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.

US Patent:

20110284994, Nov 24, 2011

Filed:

May 21, 2010

Appl. No.:

12/784706

Inventors:

David Bang - San Diego CA, US
Thomas Andrew Myers - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H01L 23/58
H01L 21/50

US Classification:

257618, 438121, 257E23002, 257E21499

Abstract:

A semiconductor die has multiple discontinuous conductive segments arranged around a periphery of the semiconductor die, and an electrically insulating barrier within discontinuities between the conductive segments. The conductive segments and the barriers form a mechanically continuous seal ring around the semiconductor die.

US Patent:

20130222060, Aug 29, 2013

Filed:

Feb 27, 2012

Appl. No.:

13/406431

Inventors:

Chi Shun Lo - San Diego CA, US
Jonghae Kim - San Diego CA, US
Wesley Nathaniel Allen - Lafayette IN, US
Chengjie Zuo - Santee CA, US
Changhan Yun - San Diego CA, US
Thomas Andrew Myers - San Diego CA, US
Prasad Srinivasa Siva Gudem - San Diego CA, US
Matthew Michael Nowak - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03H 7/38
H03F 1/00

US Classification:

330185, 333 32, 330192

Abstract:

An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit.

US Patent:

20190103653, Apr 4, 2019

Filed:

Sep 27, 2018

Appl. No.:

16/145100

Inventors:

- San Diego CA, US
Rajneesh KUMAR - San Diego CA, US
Mohammad Ali TASSOUDJI - San Diego CA, US
Darryl JESSIE - San Diego CA, US
Gurkanwal SAHOTA - San Diego CA, US
Kevin Hsi Huai WANG - San Diego CA, US
Jeong KIM, II - San Diego CA, US
Taesik YANG - San Diego CA, US
Thomas MYERS - San Diego CA, US
Neil BURNS - San Diego CA, US
Julio ZEGARRA - La Jolla CA, US
Clinton James WILBER - San Diego CA, US
Jordan SZABO - Carlsbad CA, US

International Classification:

H01Q 1/22
H01Q 1/52
H01L 23/552
H01L 23/66
H01L 23/64
H01L 23/28

Abstract:

An antenna module is described. The antenna module include a ground plane in a multilayer substrate. The antenna module also includes a mold on the multilayer substrate. The antenna module further includes a conductive wall separating a first portion of the mold from a second portion of the mold. The conductive wall is electrically coupled to the ground plane. A conformal shield may be placed on a surface of the second portion of the mold. The conformal shield is electrically coupled to the ground plane.

US Patent:

20180269585, Sep 20, 2018

Filed:

Mar 15, 2018

Appl. No.:

15/922827

Inventors:

- San Diego CA, US
Jorge FABREGA SANCHEZ - San Diego CA, US
Mohammad Ali TASSOUDJI - San Diego CA, US
Yu-Chin OU - San Diego CA, US
Zhang JIN - San Diego CA, US
Thomas MYERS - San Diego CA, US

International Classification:

H01Q 13/10
H01Q 9/04
H01Q 15/24

Abstract:

In an aspect, an apparatus may be an apparatus for wireless communication. The apparatus for wireless communication may include a transceiver, a memory, and at least one processor coupled to the memory and configured to execute instructions stored in the memory to control the transceiver. In another aspect, an apparatus may be an apparatus for wireless communication. The apparatus for wireless communication may include a patch antenna coupled to the transceiver. The patch antenna includes a patch, a ground plane substantially located with respect to the patch, a probe feed coupled to the patch, and a slot-coupled feed configured to couple to the patch.

US Patent:

20160125995, May 5, 2016

Filed:

Oct 31, 2014

Appl. No.:

14/530068

Inventors:

- San Diego CA, US
Darryl JESSIE - San Diego CA, US
Thomas Andrew MYERS - San Diego CA, US

International Classification:

H01F 19/00
H01F 17/00

Abstract:

An apparatus configured to isolate a direct current component voltage of a first circuit from a direct current component voltage of a second circuit in which the apparatus includes a first conductor and a second conductor. The first conductor has a first portion disposed to substantially enclose a first area, a second portion disposed within the first area, a third portion disposed to substantially enclose a second area, and a fourth portion disposed within the second area, the second area lacking an intersection with the first area. The second conductor is configured to be magnetically coupled to the first conductor and has a fifth portion disposed between the first portion and the second portion and a sixth portion disposed between the third portion and the fourth portion.