Thomas E Myers

US Patent:

8432237, Apr 30, 2013

Filed:

Aug 14, 2009

Appl. No.:

12/541831

Inventors:

Guy Klemens - San Diego CA, US
Nathan M Pletcher - Encinitas CA, US
Babak Nejati - San Diego CA, US
Norman L Frederick - Vista CA, US
Thomas A Myers - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H01P 5/12
H03H 7/38

US Classification:

333126, 333129, 333132

Abstract:

An output circuit with integrated impedance matching, power combining, and filtering and suitable for use with power amplifiers and other circuits is described. In an exemplary design, an apparatus may include first and second circuits (e. g. , power amplifiers) and an output circuit. The first circuit may provide a first single-ended signal and may have a first output impedance. The second circuit may provide a second single-ended signal and may have a second output impedance. The output circuit may include (i) first and second matching circuits that perform output impedance matching and filtering for the first and second circuits, (ii) a combiner (e. g. , a summing node) that combines the first and second single-ended signals to obtain a combined single-ended signal, (iii) a third matching circuit that performs impedance matching and filtering for the combined single-ended signal, and (iv) switches to route the single-ended signals to different outputs.

US Patent:

8633777, Jan 21, 2014

Filed:

Dec 1, 2009

Appl. No.:

12/628502

Inventors:

Zhang Jin - San Diego CA, US
Aristotele Hadjichristos - San Diego CA, US
Hongyan Yan - San Diego CA, US
Guy Klemens - San Diego CA, US
Maulin P. Bhagat - San Diego CA, US
Thomas Myers - San Diego CA, US
Norman L. Frederick - San Diego CA, US
Junxiong Deng - San Diego CA, US
Aleksandar Tasic - San Diego CA, US
Bhushan S. Asuri - San Diego CA, US
Mohammad Farazian - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03B 1/00

US Classification:

331167, 331117 R, 331117 FE

Abstract:

An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits.

US Patent:

7995259, Aug 9, 2011

Filed:

May 21, 2008

Appl. No.:

12/125052

Inventors:

Barry G. Broome - Carlsbad CA, US
Thomas R. Myers - Palo Alto CA, US
Leonard C. DeBenedictis - Palo Alto CA, US
David A. Dewey - Sunnyvale CA, US

Assignee:

Reliant Technologies, Inc. - Mountain View CA

International Classification:

G02B 26/08

US Classification:

3592111

Abstract:

An optical pattern generator uses a rotating component that includes a number of deflection sectors containing optical elements. Each sector deflects an incident optical beam by a substantially constant angle although this angle may vary from one sector to the next. The constant deflection angle is achieved by symmetry within the deflection sector, specifically gut-ray symmetry. The rotating component may be combined with an imaging group that produces, for example, image points, spots, or lines displaced along a line locus. The image spots can also be displaced to either side of a line, for example by introducing a tilt in the orthogonal direction or by introducing light beams at various angles to the plane of symmetry.

US Patent:

20100291888, Nov 18, 2010

Filed:

Oct 7, 2009

Appl. No.:

12/575414

Inventors:

Aristotele Hadjichristos - Cary NC, US
Puay Hoe See - San Diego CA, US
Babak Nejati - San Diego CA, US
Guy Klemens - San Diego CA, US
Norman Frederick, JR. - Vista CA, US
Gurkanwal Singh Sahota - San Diego CA, US
Marco Cassia - San Diego CA, US
Nathan Pletcher - Encinitas CA, US
Yu Zhao - San Diego CA, US
Thomas Myers - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H04B 1/04

US Classification:

4551274

Abstract:

A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels.

US Patent:

20100327976, Dec 30, 2010

Filed:

Feb 12, 2010

Appl. No.:

12/705493

Inventors:

Guy Klemens - San Diego CA, US
Thomas A. Myers - San Diego CA, US
Yu Zhao - San Diego CA, US
Babak Nejati - San Diego CA, US
Nathan M. Pletcher - Encinitas CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03F 3/16

US Classification:

330277

Abstract:

A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.

US Patent:

20110284994, Nov 24, 2011

Filed:

May 21, 2010

Appl. No.:

12/784706

Inventors:

David Bang - San Diego CA, US
Thomas Andrew Myers - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H01L 23/58
H01L 21/50

US Classification:

257618, 438121, 257E23002, 257E21499

Abstract:

A semiconductor die has multiple discontinuous conductive segments arranged around a periphery of the semiconductor die, and an electrically insulating barrier within discontinuities between the conductive segments. The conductive segments and the barriers form a mechanically continuous seal ring around the semiconductor die.

US Patent:

20120075216, Mar 29, 2012

Filed:

Sep 16, 2011

Appl. No.:

13/235158

Inventors:

Justin Phelps Black - Santa Clara CA, US
Ravindra V. Shenoy - Dublin CA, US
Evgeni Petrovich Gousev - Saratoga CA, US
Aristotele Hadjichristos - San Diego CA, US
Thomas Andrew Myers - San Diego CA, US
Jonghae Kim - San Diego CA, US
Mario Francisco Velez - San Diego CA, US
Je-Hsiung Jeffrey Lan - San Diego CA, US
Chi Shun Lo - San Diego CA, US

Assignee:

QUALCOMM MEMS TECHNOLOGIES, INC. - San Diego CA

International Classification:

G06F 3/041
H01L 21/02
H03F 3/04
H01L 27/06

US Classification:

345173, 257531, 438381, 330289, 257E21003, 257E27011

Abstract:

This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

US Patent:

20130222060, Aug 29, 2013

Filed:

Feb 27, 2012

Appl. No.:

13/406431

Inventors:

Chi Shun Lo - San Diego CA, US
Jonghae Kim - San Diego CA, US
Wesley Nathaniel Allen - Lafayette IN, US
Chengjie Zuo - Santee CA, US
Changhan Yun - San Diego CA, US
Thomas Andrew Myers - San Diego CA, US
Prasad Srinivasa Siva Gudem - San Diego CA, US
Matthew Michael Nowak - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03H 7/38
H03F 1/00

US Classification:

330185, 333 32, 330192

Abstract:

An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit.