Thomas Viet Nguyen

Address:

12189 Emory Fls Ct, Bristow, VA 20136

Phone:

7035308927

VIN:

5FNRL38707B059546

Make:

HONDA

Model:

ODYSSEY

Year:

2007

US Patent:

6410451, Jun 25, 2002

Filed:

Sep 27, 1999

Appl. No.:

09/405949

Inventors:

Thomas D. Nguyen - Campbell CA
George Mueller - San Jose CA
Peter McGrath - Roseville CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21302

US Classification:

438713, 438714, 438743, 438744, 438723, 438724, 438624

Abstract:

Improved methods and apparatus for chemically assisted etch processing in a plasma processing system are disclosed. In accordance with one aspect of the invention, improved techniques suitable for performing an etch process in the plasma processing can be realized. The invention operates to reduce the critical dimension bias that is associated with the etch process. Lower critical dimension bias provides many benefits. One such benefit is that features with higher aspect ratio can be etched correctly. In addition, several other undesired effects, e. g. , micro loading, bowing and passivation, can be curtailed using the techniques of the present invention.

US Patent:

6697553, Feb 24, 2004

Filed:

Feb 15, 2002

Appl. No.:

10/077581

Inventors:

Jyoti Kiron Bhardwaj - Cupertino CA
Robert James Brainard - Sunnyvale CA
David J. Chapman - San Jose CA
Douglas E. Crafts - San Jose CA
David Dougherty - Sunnyvale CA
Erik W. Egan - Oakland CA
James F. Farrell - San Jose CA
Mark B. Farrelly - San Jose CA
Niranjan Gopinathan - Santa Clara CA
Kenzo Ishida - Saratoga CA
David K. Nakamoto - Sunnyvale CA
Thomas Thuan Nguyen - San Jose CA
Suresh Ramalingam - Fremont CA
Steven M. Swain - San Jose CA
Sanjay M. Thekdi - Santa Clara CA
Anantharaman Vaidyanathan - San Jose CA
Hiroaki Yamada - San Jose CA
Yingchao Yan - Milpitas CA

Assignee:

JDS Uniphase Corporation - San Jose CA

International Classification:

G02B 634

US Classification:

385 37, 385 24, 385 46, 385 43

Abstract:

A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e. g. , width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

US Patent:

6733594, May 11, 2004

Filed:

Dec 21, 2000

Appl. No.:

09/747703

Inventors:

Thomas D. Nguyen - Campbell CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

B08B 300

US Classification:

134 6, 134 19, 134 26, 134 30, 134 34, 134902, 216 67, 438906, 438928, 15 211

Abstract:

A method and system for processing a wafer is disclosed. The method includes receiving a wafer having a process side and a backside. The method further includes removing un-wanted particles from the backside of the wafer to prevent gaps from forming between the backside of the wafer and a chucking surface. The method also includes performing a specific processing task on the process side of the wafer after cleaning the backside of the wafer.

US Patent:

6899109, May 31, 2005

Filed:

Mar 16, 2004

Appl. No.:

10/802647

Inventors:

Thomas D. Nguyen - Campbell CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

B08B003/00

US Classification:

134 61, 15634531, 15634532, 15634551, 15 211

Abstract:

A system for processing a wafer includes a cleaning module configured to only clean the back side of the wafer so as to remove unwanted particles therefrom before performing subsequent processing tasks on the process side of the wafer. The system also includes a processing module configured to perform processing tasks on the process side of the wafer. The processing module includes a chuck for supporting the wafer during the processing task. The system further includes a transport module configured to remove the cleaned wafer from the cleaning module, move it to the processing module and place it on the chuck of the processing module without performing any intervening manipulations during the movement.

US Patent:

6947653, Sep 20, 2005

Filed:

Oct 12, 2001

Appl. No.:

09/977065

Inventors:

Jyoti Kiron Bhardwaj - Cupertino CA, US
Robert James Brainard - Sunnyvale CA, US
David Dougherty - Sunnyvale CA, US
Erik W. Egan - Oakland CA, US
Niranjan Gopinathan - Santa Clara CA, US
David K. Nakamoto - Sunnyvale CA, US
Thomas Thuan Nguyen - San Jose CA, US
Sanjay M. Thekdi - Santa Clara CA, US
Anantharaman Vaidyanathan - San Jose CA, US
Hiroaki Yamada - San Jose CA, US
Yingchao Yan - Milpitas CA, US

Assignee:

JDS Uniphase Corporation - San Jose CA

International Classification:

G02B006/10
G02B006/13
G02F001/295

US Classification:

385129, 385 10, 385 11, 385132, 438 31

Abstract:

A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.

US Patent:

7479458, Jan 20, 2009

Filed:

Dec 15, 2005

Appl. No.:

11/305369

Inventors:

Guang-Yaw Hwang - Hsin-Shi, TW
Thomas Nguyen - Fremont CA, US
Timothy Tran - Fremont CA, US
Yu-Wei Yang - Hsin-Shi, TW

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/302

US Classification:

438714, 438725, 438740, 216 67

Abstract:

A method for etching a barrier material on a semiconductor substrate is disclosed. The method includes placing the substrate in a plasma processing chamber of the plasma processing system, wherein the substrate includes the barrier material and a low-k material, and wherein the barrier material and a low-k material are configured to be exposed to a plasma. The method also includes flowing an etchant gas mixture, including CHF from about 4% to about 8% of a plasma gas flow, into the plasma processing chamber, wherein the etchant gas mixture is configured to etch the barrier material at a first etch rate, the etchant gas mixture is configured to etch the low-k material at a second etch rate, wherein the first etch rate is substantially greater than the second etch rate. The method further includes striking a plasma from the etchant source gas; and etching the barrier layer and the low-k layer.

US Patent:

7696836, Apr 13, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/929679

Inventors:

Thomas Nguyen - Fremont CA, US
Jerry Martinson - San Jose CA, US

Assignee:

Aruba Networks, Inc. - Sunnyvale CA

International Classification:

H01P 5/00
H03H 7/00

US Classification:

333 24R, 333177

Abstract:

Improved coupler for Ethernet over twisted pair. An improved coupler has a first common mode choke for connecting an Ethernet PHY to the primary winding of a transformer. The secondary winding of the transformer connects through a second common mode choke for connection to a twisted pair line. In one embodiment, the first common mode choke, transformer, and second common mode choke are placed in the same package. In a second environment, a plurality of choke-transformer-choke units are placed in the same package. In a third embodiment, the plurality of choke-transformer-choke units may be integrated into a connector. Pairs of the second common mode chokes may share cores.

US Patent:

D627345, Nov 16, 2010

Filed:

Jan 29, 2009

Appl. No.:

29/331667

Inventors:

Gururaj Govindasamy - San Ramon CA, US
Jonathan Burke - Berkeley CA, US
Kenneth Mak - San Francisco CA, US
Thomas Nguyen - Fremont CA, US

Assignee:

Aruba Networks, Inc. - Sunnyvale CA

International Classification:

1402

US Classification:

D14356, D14240