Thomas O Perry

US Patent:

45312109, Jul 23, 1985

Filed:

Jun 22, 1983

Appl. No.:

6/506758

Inventors:

Thomas J. Perry - Phoenix AZ

Assignee:

GTE Automatic Electric Incorporated - Northlake IL

International Classification:

H04T 306

US Classification:

370100

Abstract:

In a telecommunications switching system, which has a switching network connected to a number of asynchronous digital spans, a digital span reframing circuit continuously reframes and resynchronizes each of the digital spans that are detected as lacking proper framing. The digital span reframing circuit realigns both framing and super framing, TS bits and FS bits, for proper digital span reception.

US Patent:

57296782, Mar 17, 1998

Filed:

Mar 4, 1996

Appl. No.:

8/611984

Inventors:

Jeffrey Glenn Hunt - Glendale AZ
Thomas Jay Perry - Phoenix AZ
Michael Gilbert - Glendale AZ
Randall Lew Brown - Phoenix AZ
James B. Southway - Glendale AZ

Assignee:

AG Communication Systems Corporation - Phoenix AZ

International Classification:

G06F 1100

US Classification:

39518319

Abstract:

A bus monitor system comprises eight identical programmable monitor circuits that are each connected to a monitored bus and to a local 16-bit event bus. There are three interfaces to the event bus within each monitor circuit. One interface asserts a predetermined bit pattern on the event bus when match conditions occur between bit patterns on the monitored bus and predetermined bit patterns stored in monitor circuit registers. A second interface asserts a signal on an external pin when bit patterns on the event bus match a predetermined bit pattern stored in a monitor circuit register. A third interface asserts a predetermined bit pattern on the event bus when an external device has asserted a signal on an external pin. Each monitor circuit is capable of reading and asserting any of the bits of the event bus. The event bus is used to enable or disable monitor circuit interfaces.

US Patent:

45947139, Jun 10, 1986

Filed:

Dec 22, 1983

Appl. No.:

6/564135

Inventors:

Thomas J. Perry - Phoenix AZ
Muhammad I. Khera - Glendale AZ

Assignee:

GTE Automatic Electric Inc. - Northlake IL

International Classification:

G06F 1100

US Classification:

371 49

Abstract:

A receive data reformatter for a telecommunications switching system is shown for disassembling a data message to a plurality of 8-bit data bytes. The receive data reformatter is comprised of a parallel to serial converter which receives the data message one byte at a time which it subsequently outputs serially. A horizontal parity check circuit receives the serial data and is arranged to output an error signal when an error in parity is detected. A serial to parallel converter, connected to the serial output of the parallel to serial converter, receives the serial data and assembles the serial data into parallel form. A write buffer connected to the serial to parallel converter receives the assembled parallel data when eight data bits have been accumulated in the serial to parallel converter. The thus formed data byte is output to a peripheral processor of the telecommunications switching system.

US Patent:

45984042, Jul 1, 1986

Filed:

Dec 22, 1983

Appl. No.:

6/564137

Inventors:

Thomas J. Perry - Phoenix AZ
Muhammad I. Khera - Glendale AZ

Assignee:

GTE Automatic Electric Inc. - Northlake IL

International Classification:

G06F 1100

US Classification:

371 49

Abstract:

A formatted data message for conveying control information from the peripheral processor of one telecommunications switching system to the peripheral processor of at least one other telecommunications switching system is provided. The data message format comprises a first control work including a plurality of control bits, a data bit and a parity bit for the first control word and a plurality of data words, each data word including a parity bit. The data words contain control information to be conveyed to the receiving peripheral processor. A parity word is included which provides parity for an associated plurality of the preceding data and control words.

US Patent:

43564046, Oct 26, 1982

Filed:

May 26, 1981

Appl. No.:

6/267165

Inventors:

Joseph A. Comfort - Phoenix AZ
Thomas J. Perry - Phoenix AZ
Michel Loos - Phoenix AZ

Assignee:

GTE Automatic Electric Labs Inc. - Northlake IL

International Classification:

H01H 1914

US Classification:

307115

Abstract:

This is a circuit for use to increase the number of bus circuit boards in a closed loop bus configuration. This circuit detects which bus circuit board is the last circuit board equipped in a closed loop configuration and closes the bus at that circuit, without requiring wiring changes or "dummy" circuit boards.

US Patent:

45802432, Apr 1, 1986

Filed:

Sep 14, 1983

Appl. No.:

6/531986

Inventors:

Robert E. Renner - Glendale AZ
Thomas J. Perry - Phoenix AZ

Assignee:

GTE Automatic Electric Incorporated - Northlake IL

International Classification:

G06F 1342
H04L 700

US Classification:

364900

Abstract:

The present invention provides for synchronizing signals transmitted to two duplex copies of hardware from a common source. Signals sent from the source to the duplex copies of hardware may arrive asynchronously at the two copies and require synchronization. In addition, the duplex hardware may be validly operated in the simplex mode of operation, which requires no synchronization of the two hardware copies.

US Patent:

45077800, Mar 26, 1985

Filed:

Jun 22, 1983

Appl. No.:

6/506571

Inventors:

Thomas J. Perry - Phoenix AZ

Assignee:

GTE Automatic Electric Incorporated - Northlake IL

International Classification:

H04J 300

US Classification:

370100

Abstract:

In a telecommunications switching system, which has a switching network connected to a number of asynchronous digital spans, a digital span frame detection circuit continuously monitors the framing of each of the digital spans. The digital span frame detection circuit checks for both proper framing and super framing, TS bits and FS bits. An ordered examination of each of the number of digital spans will occur. Any digital span which lacks proper framing or super framing will be marked for subsequent processing. These markings will be scanned and submitted for reframing in an ordered fashion.

US Patent:

46774360, Jun 30, 1987

Filed:

Apr 27, 1984

Appl. No.:

6/604762

Inventors:

Christopher M. Burlingame - Northlake IL
Thomas J. Perry - Phoenix AZ

Assignee:

GTE Communication Systems Corporation - Phoenix AZ

International Classification:

H04Q 100

US Classification:

34082579

Abstract:

An arrangement for connecting an array of individual electronic elements into a readily expandable matrix. The arrangement comprises a plurality of matrix slices with each slice including a set number of electronic elements as well as a row and a column buffer. The electronic elements of each matrix slice are diagonally connected to the elements of the adjacent matrix slice.