Thomas H Peterson

US Patent:

6275906, Aug 14, 2001

Filed:

May 20, 1999

Appl. No.:

9/315487

Inventors:

Jose Melanio Nunez - Austin TX
Thomas Albert Peterson - Austin TX
Marie Jeannette Sullivan - Leander TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1202

US Classification:

711141

Abstract:

A memory subsystem for use with a multiprocessor computer system. The memory subsystem includes an operation block adapted for queuing an operation that misses in an L1 cache of a multiprocessor. The multiprocessor is comprised of a set of processors, preferably fabricated on a single semiconductor substrate and packaged in a single device package. The memory subsystem further includes an arbiter that is configured to receive external snoop operations from a bus interface unit and a queued operation from the operation block. The arbiter is configured to select and initiate one of received operations. Coherency is maintained by forwarding the address associated with the operation selected by the arbiter to each of a plurality of coherency units. In this manner, external and internal snoop addresses are arbitrated at a single point to produce a single subsystem snoop address that is propagated to each coherency unit. Preferably, the operation block includes a load miss block suitable for queuing load type operations and a store miss block suitable for queuing store type operations.

US Patent:

20170025892, Jan 26, 2017

Filed:

Apr 27, 2016

Appl. No.:

15/139407

Inventors:

Daniel K. Van Ostrand - Pflugerville TX, US
Thomas L. Peterson - Fairfax Station VA, US

International Classification:

H02J 13/00
G05B 15/02

Abstract:

A portable electrical energy power node is provided. The power node includes first and second input power terminals and first and second output power terminals. The input power terminals are adapted for receiving a source of electrical power and the output terminals are adopted for connecting to a load. A first power line connects the first input terminal to the first output terminal, a second power line connects the second input terminal to the input side of a circuit interrupter and a third power line connects the output side of the circuit interrupter to the second output terminal. The circuit interrupter selectively interrupts the connection between the second input terminal and the second output terminal in accordance with a fault sensor and a control unit.