Thomas J Schaefer
age ~74
from Redwood City, CA
- Also known as:
-
- Thomas John Schaefer
- Thomas Barbara Schaefer
- Tom Schaefer
- Thomas J Schaeffer
- Thomas J Zan
- Thomas J Schafer
- Phone and address:
-
2024 Whipple Ave, Redwood City, CA 94062
6509966442
Thomas Schaefer Phones & Addresses
- 2024 Whipple Ave, Redwood City, CA 94062 • 6509966442
- San Mateo, CA
- Irving, TX
- San Ramon, CA
- 4600 Tassajara Rd, Dublin, CA 94568
- Andover, MA
- West Des Moines, IA
- Solon, OH
- 2024 Whipple Ave, Redwood City, CA 94062
Us Patents
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Levelized Logic Simulator With Fenced Evaluation
view source -
US Patent:50620673, Oct 29, 1991
-
Filed:Mar 15, 1989
-
Appl. No.:7/324283
-
Inventors:Thomas J. Schaefer - Cupertino CA
Robert D. Shur - Los Altos CA -
Assignee:VLSI Technology, Inc. - San Jose CA
-
International Classification:G06F 1560
G06F 1520 -
US Classification:364578
-
Abstract:A simulator for a levelized logic circuit reduces the number of evaluations required. The simulator associates certain lists of signals, called fences, with each component of a logic circuit. A fence is evaluated to determine whether it is active or inactive. Active fences contain signals which have charged since a previous evaluation. Components for active fences are then evaluated by the simulator. Fences are formed by starting with a seed set of signals. If all of the input signals to a component are in one or more fences, a final fence for a component is formed which is the union of the one or more fences. Only signals which can cause an output change on a component are included in fences.
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Method For Estimating Interconnect Delays In Integrated Circuits
view source -
US Patent:56173253, Apr 1, 1997
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Filed:Sep 4, 1992
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Appl. No.:7/941763
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Inventors:Thomas J. Schaefer - Cupertino CA
-
Assignee:VLSI Technology, Inc. - San Jose CA
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International Classification:G06F 1750
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US Classification:364488
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Abstract:A method for predicting circuit interconnect delays in circuits of the type that have a driving device attached to an input node of a network having a plurality of nodes, with the driving device changing states from time to time so as to impose on the network a voltage different from the previous voltage of the network. The method includes the steps of estimating the waveform on the input node and predicting the waveforms on other nodes of the network on the basis of the estimated input node waveform.
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Automated Optimization Of Hierarchical Netlists
view source -
US Patent:59562579, Sep 21, 1999
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Filed:Mar 31, 1993
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Appl. No.:8/040738
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Inventors:Arnold Ginetti - Antibes, FR
Thomas J. Schaefer - Cupertino CA
Robert D. Shur - Los Altos CA
Christopher H. Kingsley - San Jose CA -
Assignee:VLSI Technology, Inc. - San Jose CA
-
International Classification:G06F 1750
-
US Classification:364490
-
Abstract:A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.
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Enhanced Dynamic Programming Method For Technology Mapping Of Combinational Logic Circuits
view source -
US Patent:57870101, Jul 28, 1998
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Filed:Jun 6, 1997
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Appl. No.:8/870860
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Inventors:Thomas J. Schaefer - Cupertino CA
Robert D. Shur - Los Altos CA -
International Classification:G06F 1500
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US Classification:364489
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Abstract:A circuit optimization method in which a set of cost functions are stored for each node that indicate the cost of getting signals to that node and the cost of a gate at that node. By "cost", is meant some figure of merit, such as: the maximal delay for a signal to arrive at a node G; or the area of the elements needed to produce the signal at node G. These cost functions enable the circuit to be optimized without the need for a pattern library and the pattern matching process that is typical of other optimization processes, such as the DAGON Node Tiling Procedure.
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Buffer Circuit Design Using Back Track Searching Of Site Trees
view source -
US Patent:54023564, Mar 28, 1995
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Filed:Apr 2, 1992
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Appl. No.:7/862895
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Inventors:Thomas J. Schaefer - Cupertino CA
Robert D. Shur - Los Altos CA -
Assignee:VLSI Technology, Inc. - San Jose CA
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International Classification:G06F 1560
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US Classification:364489
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Abstract:A buffer circuit for fanning out a source signal to a plurality of terminals of specified polarities in accordance with specified time constraints is designed by an automated method in which a circuit template is specified in terms of a tree structure. The terminals are ordered in increasing order of required arrival times of the source signal at each of the terminals. A first terminal in a resulting order is assigned to a highest-level potential terminal site of a same polarity as said first terminal, and buffers on a signal path between said first terminal and the source signal are sized so as to satisfy, if possible, a required arrival time of the source signal at said first terminal. So long as required times of arrival are met, additional terminals are placed in like manner. The method proceeds as far as possible using a straight forward assignment procedure of terminals to potential terminal sites, then backtracks, undoing so much of the previous assignments as necessary and making incremental adjustments to allow the method to proceed further if possible.
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Event-Controlled Lcc Stimulation
view source -
US Patent:50688120, Nov 26, 1991
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Filed:Jul 18, 1989
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Appl. No.:7/381548
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Inventors:Thomas J. Schaefer - Cupertino CA
Robert D. Shur - Los Altos CA -
Assignee:VLSI Technology, Inc. - San Jose CA
-
International Classification:G06F 1518
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US Classification:364578
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Abstract:A method for simulating a levelized logic circuit including an event-controlled feature for marking components to be reevaluated. An evaluation list is formed which lists signals and corresponding components of the logic circuit which are to be reevaluated. A second list is formed of each component and its corresponding output signals. The external input signals are also listed. Each external input signal is tested for change from a previous evaluation and, if so, the corresponding components in the re-evaluation list are marked for reevaluation. Each component, in levelized order, is then tested to determine whether that component is marked for re-evaluation and, if so, that component is re-evaluated and unmarked, and each signal in the component output signal list which has a non-empty re-evaluation list is tested to determine if the value of the signal has changed since the previous evaluation and, if so, all of the components in that signal's reevaluation list are marked for re-evaluation. Evaluation marks are stored as a marking bit in a memory location associated with a component. The components associated with frequently changing input signals are evaluated without setting or testing their evaluation marks.
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System And Method For Setting Capacitive Constraints On Synthesized Logic Circuits
view source -
US Patent:51970155, Mar 23, 1993
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Filed:Dec 20, 1990
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Appl. No.:7/631600
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Inventors:Mark R. Hartoog - Los Gatos CA
Thomas J. Schaefer - Cupertino CA
Robert D. Shur - Los Altos CA -
Assignee:VLSI Technology, Inc. - San Jose CA
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International Classification:G06F 1560
-
US Classification:364490
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Abstract:In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits's nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node. Then, the following steps are repeated until changes in the computed routing difficulty value for the entire circuit meet predefined criteria.
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System And Method For Synthesizing Logic Circuits With Timing Constraints
view source -
US Patent:54023572, Mar 28, 1995
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Filed:Dec 2, 1991
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Appl. No.:7/801793
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Inventors:Thomas J. Schaefer - Cupertino CA
Robert D. Shur - Los Altos CA -
Assignee:VLSI Technology, Inc. - San Jose CA
-
International Classification:G06F 1560
-
US Classification:364490
-
Abstract:In a computer aided design system, a netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The automatic circuit layout synthesis process begins by assigning an initial capacitance value to each node. Next, a routing difficulty value is computed, this value comprises a sum of routing difficulty values associated with each of the nodes in the integrated circuit. Capacitance values for the integrated circuit are then adjusted so as to reduce the computed routing difficulty. Finally, the netlist and adjusted capacitance values are passed to a silicon compiler for automatic placement and routing of a circuit having capacitance values not exceeding the adjusted capacitance values.
Amazon
LooseLeaf for Advanced Accounting
view sourceThe approach used by Hoyle, Schaefer, and Doupnik in the new edition allows students to think critically about accounting, just as they will do while preparing for the CPA exam and in their future careers. With this text, students gain a well-balanced appreciation of the accounting profession. As Ho...
Author
Joe Ben Hoyle, Thomas Schaefer, Timothy Doupnik
Binding
Loose Leaf
Pages
976
Publisher
McGraw-Hill Education
ISBN #
1259444953
EAN Code
9781259444951
ISBN #
7
Advanced Accounting
view sourceThe approach used by Hoyle, Schaefer, and Doupnik in the new edition allows students to think critically about accounting, just as they will do while preparing for the CPA exam and in their future careers. With this text, students gain a well-balanced appreciation of the Accounting profession. As Ho...
Author
Joe Ben Hoyle, Thomas Schaefer, Timothy Doupnik
Binding
Hardcover
Pages
928
Publisher
McGraw-Hill Education
ISBN #
0077862228
EAN Code
9780077862220
ISBN #
6
Advanced Accounting
view sourceThe approach used by Hoyle, Schaefer, and Doupnik in the new edition allows students to think critically about accounting, just as they will do while preparing for the CPA exam and in their future careers. With this text, students gain a well-balanced appreciation of the Accounting profession. As Ho...
Author
Joe Ben Hoyle, Thomas Schaefer, Timothy Doupnik
Binding
Hardcover
Pages
912
Publisher
McGraw-Hill/Irwin
ISBN #
0078025400
EAN Code
9780078025402
ISBN #
5
Loose Leaf Advanced Accounting with Connect Access Card
view sourceThe approach used by Hoyle, Schaefer, and Doupnik in the new edition allows students to think critically about accounting, just as they will do while preparing for the CPA exam and in their future careers. With this text, students gain a well-balanced appreciation of the Accounting profession. As Ho...
Author
Joe Ben Hoyle, Thomas Schaefer, Timothy Doupnik
Binding
Loose Leaf
Publisher
McGraw-Hill Education
ISBN #
1259184749
EAN Code
9781259184741
ISBN #
2
Fundamentals of Advanced Accounting
view sourceFundamentals of Advanced Accounting, 5th edition, is ideal for those schools wanting to cover 12 chapters in their advanced accounting course. This brief yet concise text allows students to think critically about accounting, just as they will do preparing for the CPA exam. With this text, students g...
Author
Joe Ben Hoyle, Thomas Schaefer, Timothy Doupnik
Binding
Hardcover
Pages
640
Publisher
McGraw-Hill Education
ISBN #
0078025397
EAN Code
9780078025396
ISBN #
1
Study Guide & Working Papers to accompany Advanced Accounting
view sourceAuthor
Joe Ben Hoyle, Thomas Schaefer, Timothy Doupnik
Binding
Paperback
Pages
256
Publisher
McGraw-Hill/Irwin
ISBN #
0077268040
EAN Code
9780077268046
ISBN #
10
Fundamentals of Advanced Accounting
view sourceFundamentals of Advanced Accounting, 6th edition, is ideal for those schools wanting to cover 12 chapters in their advanced accounting course. This brief yet concise text allows students to think critically about accounting, just as they will do preparing for the CPA exam. The text continues to show...
Author
Joe Ben Hoyle, Thomas Schaefer, Timothy Doupnik
Binding
Hardcover
Pages
648
Publisher
McGraw-Hill Education
ISBN #
0077862236
EAN Code
9780077862237
ISBN #
4
Loose Leaf for Advanced Accounting
view sourceAuthor
Joe Ben Hoyle, Thomas Schaefer, Timothy Doupnik
Binding
Paperback
Pages
976
Publisher
McGraw-Hill Education
ISBN #
1260008711
EAN Code
9781260008715
ISBN #
3
Name / Title
Company / Classification
Phones & Addresses
SPI ENTERPRISES, LTD
PERSONAL REFLECTIONS BY JACQUELINE, LTD
TOM SCHAEFER PLUMBING, INC
SCHAEFER FAMILY ENTERPRISES, LLC
UNITED PLANNERS' FINANCIAL SERVICES OF AMERICA, A LIMITED PARTNERSHIP
TJCS FINANCIAL SERVICES, LLC
Chief Operating Offi
KATY RESOURCES LLC
Oil/Gas Exploration Services
Oil/Gas Exploration Services
4809 Cole Ave STE 108, Dallas, TX 75205
811 Main St STE 14, Houston, TX 77002
2145269700
811 Main St STE 14, Houston, TX 77002
2145269700
President, Secretary
HONDO CLUB, INC
Membership Sport/Recreation Club
Membership Sport/Recreation Club
3796 Chatham Ct Dr, Addison, TX 75001
Medicine Doctors
Thomas L. Schaefer
view sourceSpecialties:
Family Medicine, Internal Medicine - Geriatrics
Work:
Thomas L Schaefer MD
6011 Baptist Rd STE 200, Pittsburgh, PA 15236
4128511200 (phone), 4128511234 (fax)
6011 Baptist Rd STE 200, Pittsburgh, PA 15236
4128511200 (phone), 4128511234 (fax)
Education:
Medical School
University of Pittsburgh School of Medicine
Graduated: 1983
University of Pittsburgh School of Medicine
Graduated: 1983
Procedures:
Allergen Immunotherapy
Arthrocentesis
Destruction of Benign/Premalignant Skin Lesions
Electrocardiogram (EKG or ECG)
Vaccine Administration
Arthrocentesis
Destruction of Benign/Premalignant Skin Lesions
Electrocardiogram (EKG or ECG)
Vaccine Administration
Conditions:
Acne
Acute Pharyngitis
Acute Sinusitis
Allergic Rhinitis
Anemia
Acute Pharyngitis
Acute Sinusitis
Allergic Rhinitis
Anemia
Languages:
English
Description:
Dr. Schaefer graduated from the University of Pittsburgh School of Medicine in 1983. He works in Pittsburgh, PA and specializes in Family Medicine and Internal Medicine - Geriatrics. Dr. Schaefer is affiliated with Jefferson Hospital.
Resumes
Senior Director
view sourceLocation:
2024 Whipple Ave, Redwood City, CA 94062
Industry:
Mechanical Or Industrial Engineering
Work:
Sage Human Capital Jan 2013 - May 2016
Vice President of Recruiting
Saveenergy123.Com Jan 2011 - Jan 2014
Chief Executive Officer
Digital Fuel Feb 2005 - Dec 2010
Executive Vice President Marketing
I2 Technologies Apr 1997 - Jan 2005
General Manager, Srm Business Unit
Aspect Development Apr 1997 - Jun 2000
Managing Director, Energy and Process Business Unit
Vice President of Recruiting
Saveenergy123.Com Jan 2011 - Jan 2014
Chief Executive Officer
Digital Fuel Feb 2005 - Dec 2010
Executive Vice President Marketing
I2 Technologies Apr 1997 - Jan 2005
General Manager, Srm Business Unit
Aspect Development Apr 1997 - Jun 2000
Managing Director, Energy and Process Business Unit
Education:
Michigan State University
Master of Business Administration, Masters Michigan State University - the Eli Broad College of Business
Masters, Business Administration, Marketing, Finance Northern Illinois University
Bachelors, Bachelor of Science, Mechanical Engineering
Master of Business Administration, Masters Michigan State University - the Eli Broad College of Business
Masters, Business Administration, Marketing, Finance Northern Illinois University
Bachelors, Bachelor of Science, Mechanical Engineering
Skills:
Saas
Start Ups
Strategic Partnerships
Product Management
Strategy
Enterprise Software
Business Development
Digital Marketing
Product Development
Management
Crm
Sales Operations
Product Marketing
Demand Generation
Lead Generation
Sales Management
Analytics
New Business Development
Sales
Marketing
Leadership
Go To Market Strategy
Social Media Marketing
Professional Services
Software Consulting
Management Consulting
Selling
Executive Management
Outsourcing
International Sales
E Commerce
Brand Management
Mergers and Acquisitions
Consulting
Mobile Devices
Marketing Management
Online Advertising
B2B Marketing
Online Marketing
Product Launch
Consultative Selling
Entrepreneurship
Strategic Planning
Business Alliances
Cross Functional Team Leadership
Business Strategy
International Sales and Marketing
Driving Revenue
Product Vision
Solution Selling
Start Ups
Strategic Partnerships
Product Management
Strategy
Enterprise Software
Business Development
Digital Marketing
Product Development
Management
Crm
Sales Operations
Product Marketing
Demand Generation
Lead Generation
Sales Management
Analytics
New Business Development
Sales
Marketing
Leadership
Go To Market Strategy
Social Media Marketing
Professional Services
Software Consulting
Management Consulting
Selling
Executive Management
Outsourcing
International Sales
E Commerce
Brand Management
Mergers and Acquisitions
Consulting
Mobile Devices
Marketing Management
Online Advertising
B2B Marketing
Online Marketing
Product Launch
Consultative Selling
Entrepreneurship
Strategic Planning
Business Alliances
Cross Functional Team Leadership
Business Strategy
International Sales and Marketing
Driving Revenue
Product Vision
Solution Selling
Languages:
English
Spanish
Spanish
Executive Vice President
view sourceLocation:
San Francisco, CA
Industry:
Computer Software
Work:
Digital Fuel since Feb 2005
EVP
EVP
Thomas Nwosu Schaefer Schaefer
view source
Thomas Schaefer
view source
Thomas G Navair Schaefer
view sourceIsbn (Books And Publications)
Fundamentals of Advanced Accounting: Working Papers
view sourceAuthor
Thomas Schaefer
ISBN #
0072871172
Classmates
Thomas Faragoi (Schaefer)
view sourceSchools:
alan b. shepard h.s. Palos Heights IL 1994-1998
Community:
Mark Peacock, Christopher Clark, Scott Zirkel, John Matuszewski, Mario Robinson, Cathy Barta, Miss Mick, Liz Sibrava, Nader Sandoka, Tre' White, Christine Jackson, Cryatal Woods
Biography:
Life
I retired as a Captain in the 21st District, and now I am selling Real Estate ...
Thomas Schaefer
view sourceSchools:
Totino-Grace High School Fridley MN 1981-1985
Community:
Jolene Hendrickson, Allison Gaudette, Sarah Kellar
Thomas Schaefer
view sourceSchools:
Grand Blanc High School Grand Blanc MI 1992-1996
Community:
Brenda Lasley, Eldon Brzak
Thomas Schaefer
view sourceSchools:
Union High School Dugger IN 1996-2000
Community:
Rhonda Landis, Mark Everett
Thomas Schaefer
view sourceSchools:
Cleveland High School Cleveland TN 1991-1995
Community:
Brad Blackburn, Tina Davis
Thomas Schaefer
view sourceSchools:
St. John's Cathedral High School Milwaukee WI 1956-1960
Community:
Consuella Newton, Dean Milano, Ron Anderson, James Purvis, Thomas Scholz
Thomas Schaefer
view sourceSchools:
St. Francis High School Milwaukee WI 1970-1974
Thomas Schaefer (Kuehmich...
view sourceSchools:
Nicolet High School Glendale WI 1978-1982
Community:
Liza Milburn, Annemarie Nedwek, Brian Blackburn, Ken Kovacic
Thomas Dean Schaefer
view source
Thomas J. Schaefer
view source
Thomas Arthur Schaefer
view source
Thomas Adam Schaefer
view source
Thomas Schaefer
view source- Cached
Plaxo
Thomas Schaefer
view sourceIMC InteractiveMediaConsulting GmbH
Thomas Schaefer
view sourceTrafford, pa
Thomas Schaefer
view sourceEagan, MN
Thomas Schaefer
view sourceCincinnati Gentlemen
Youtube
Flickr
Googleplus
Thomas Schaefer
Education:
Greenon
Thomas Schaefer
Work:
Hermes
Thomas Schaefer
Tagline:
Witty Tagline
Thomas Schaefer
Bragging Rights:
Uni und 2 Ehefrauen überstanden, lebe immer noch, 1 toller Sohn
Thomas Schaefer
Thomas Schaefer
Thomas Schaefer
Tagline:
Tactical Mismanagement
Thomas Schaefer
News
Volkswagen workers hold 2-hour strikes to push back against proposed pay cuts and plant closures
view source- higher costs and increasing competition from Chinese automakers. Volkswagen built factories to supply a European car market of 16 million in annual vehicle sales, but now faces demand for around 14 million, Volkswagen brand head Thomas Schaefer was quoted as saying in the Welt am Sonntag newspaper.
- Date: Dec 02, 2024
- Category: Business
- Source: Google
Luxembourg Takes Its Post-Brexit Banking Pitch to Frankfurt
view source- Thomas Schaefer, finance minister for Frankfurts home state of Hesse, said at a conference in the city that state Premier Volker Bouffier is in New York to discuss with major U.S. banks how they can retain access to the EU market. LuxembourgFinance MinisterPierre Gramegna told the same conference
- Date: Nov 14, 2016
- Category: Business
- Source: Google
Other Social Networks
Thomas Schaefer Google+
view sourceNetwork:
GooglePlus
Thomas Schaefer has not filled out his profile yet. - Cached
Get Report for Thomas J Schaefer from Redwood City, CA, age ~74