Thomas W Spencer

US Patent:

6880047, Apr 12, 2005

Filed:

Mar 28, 2003

Appl. No.:

10/401459

Inventors:

Thomas Vincent Spencer - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F012/08

US Classification:

711142, 711118

Abstract:

In a processor module having a local software visible data memory and a write through cache connected to an external memory space external to the processor module over a bus, a method and apparatus for supplementing the local software visible data memory utilizing the write through cache is disclosed which may comprise: a processor bus interface and memory management unit adapted to detect a processor write operation to a preselected location in the external memory space that is not currently a cached address line, that will cause a cache miss, to decode the write operation to the preselected external memory space location as a RAM emulation write operation and to place in the cache pseudo data at the respective address line in the cache, without executing a fetch and store from the actual external memory location in response to the cache miss. The method and apparatus may further comprise the processor bus interface and memory management unit further adapted to subsequently ignore the write through command from the processor when the processor writes to the address without a cache miss. The external memory space may include a cacheable portion of external memory space and a non-cacheable portion of the external memory space; and, the preselected external memory space may be located within the cacheable portion of the external memory space.

US Patent:

6912610, Jun 28, 2005

Filed:

Mar 28, 2003

Appl. No.:

10/402182

Inventors:

Thomas Vincent Spencer - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F009/00
G06F009/46
G06F009/50
G06F013/38

US Classification:

710240, 718100

Abstract:

A data processing module having a central processing unit and a task management control method and apparatus is disclosed which may comprise: a plurality of task identifiers adapted to identify a task requesting service by the central processing unit; an arbitration system external to the central processing unit adapted to select a task identifier from one of the plurality of task identifiers and to provide to the central processing unit the location of data or at least one instruction, which location is determined by the identity of the task identifier and to provide to the central processing unit the location of at least one instruction to initiate processing of the task, comprising: arbitration value determination logic adapted to determine at least one arbitration value of each task identifier requesting service; arbitration logic adapted to select a task identifier requesting service based upon the at least one arbitration value for each task identifier requesting service.

US Patent:

7058735, Jun 6, 2006

Filed:

Jun 2, 2003

Appl. No.:

10/452330

Inventors:

Thomas Vincent Spencer - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 13/00

US Classification:

710 24, 710 6, 710 22, 710 52, 712225, 712245

Abstract:

An apparatus for local direct memory access control includes a processor unit for generating a direct memory access designator when needed data is not available and continuing processing which does not require the unavailable data. A memory access designator holder receives the memory access designator, and a local data memory access controller performs a data memory access transaction in accordance with the content of a descriptor. Staging registers hold components of a data memory access designator and transfer the components to a selected portion of the data memory access designator holder. The data memory access controller transfers the contents of the staging registers to the data memory access designator holder when one of the staging registers is written to by the processor unit. The processor unit stalls if a write to the staging register occurs when the data memory access designator holders contain a data memory access designator, and ceases the stall when one of the plurality of data memory access designator holders ceases to contain a data memory access designator.

US Patent:

8255607, Aug 28, 2012

Filed:

Nov 5, 2009

Appl. No.:

12/613390

Inventors:

Marc Timothy Jones - Costa Mesa CA, US
Murthy Kompella - Costa Mesa CA, US
Thomas Vincent Spencer - Costa Mesa CA, US
Carl Joseph Mies - Costa Mesa CA, US
Sammy Dwayne Sawyer - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 13/36
G06F 13/00

US Classification:

710316

Abstract:

Described herein is an improved mechanism for bridging between SAS and SATA drives based upon existing SAS expanders in a SAS domain. In particular, a bridge capable of translating between SAS and SATA protocols is embedded in or coupled to an expander. When a SAS initiator request is received at the expander, the expander can route the request, based on a routing table, either directly to a destination SAS device or to the bridge for necessary translation before it is transmitted to a destination SATA drive. The routing table includes corresponding relationships between all SAS addresses and Phys through which those SAS and SATA devices are attached to the expander. SATA devices can be virtualized in the expander through a few assigned addresses in the routing table in a SAS discovery process.