Thomas C Stockebrand

US Patent:

40719103, Jan 31, 1978

Filed:

Nov 8, 1976

Appl. No.:

5/739670

Inventors:

Thomas C. Stockebrand - Albuquerque NM
Russell C. Doane - Framingham MA
Michael D. Morganstern - Wayland MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 312
G06F 314
G06K 1500

US Classification:

364900

Abstract:

A video terminal system having a plurality of distinct output devices providing humanly perceivable, alphanumeric information is disclosed. The video terminal processes and transfers the binary representations of each alphanumeric character to a character generator. A dot matrix corresponding to the character is provided by the character generator and is time-multiplexed so as to be time-shared by each of the output devices without the requirement for specialized circuitry and with minimal time degradation. The distinct output devices may be video displays and hard copy printers which display alphanumeric characters for a complete line, the video display devices receiving each complete line of characters in a predetermined time period and the printer devices receiving a slice of each character for a line upon request.

US Patent:

48518344, Jul 25, 1989

Filed:

Jun 29, 1987

Appl. No.:

7/068728

Inventors:

Thomas C. Stockebrand - Albuquerque NM
Joel D. Kaufman - Albuquerque NM
Earle R. Vicery - Albuquerque NM

Assignee:

Digital Equipment Corp. - Maynard MA

International Classification:

G09G 102

US Classification:

340801

Abstract:

The present system includes, in a preferred embodiment, a plurality of bit map memory units which together define a large bit map memory. For each bit map memory unit there is also included a mask means and four extended shift registers. The shift registers can be loaded in parallel with pixel information through bidirectional data transmission channels which include bidirectional mask means. The pixel information can be routed through said bidirectional mask means to different address locations, or to the same address location, with certain of the pixel bits removed by the mask means. The shift registers have both serial and parallel input and output means and are clocked at different speeds to accommodate different peripherals. At least a first shift register is designed to be serially read out at a relatively high rate which can be advantageously used by a video display device or the like. Information signals from the other shift registers are transferred at high speed (in parallel) into and out of the large bit map memory to said first shift register whereby pixel information signals are settled down before being routed from said first shift register.