Thomas J Thomas

US Patent:

6538497, Mar 25, 2003

Filed:

Mar 27, 2001

Appl. No.:

09/819135

Inventors:

Thomas P. Thomas - Hillsboro OR
Ian A. Young - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G05F 156

US Classification:

327543, 327541, 307 44, 323313

Abstract:

A method and apparatus for maintaining a stable power supply voltage. The method comprises using a power supply to provide power at a power supply voltage to a plurality of semiconductor devices. The power supply voltage is nominally at an optimal power supply voltage. A fast increase in the current can cause a drop in the supply voltage, since the high rate of change in current is through the package inductance. The power supply voltage is monitored. Further, a supplemental higher voltage power supply is used to boost the power supply voltage to substantially the optimal power supply voltage if the power supply voltage decreases by a threshold value.

US Patent:

6650161, Nov 18, 2003

Filed:

Dec 28, 2000

Appl. No.:

09/751942

Inventors:

Thomas P. Thomas - Hillsboro OR
Ian A. Young - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 300

US Classification:

327291, 327551, 327293

Abstract:

A clock distribution network for an integrated circuit is disclosed. The network includes a plurality of inverters that distribute a clock signal. The inverters are powered by a power supply. The power supply is supplied to the inverters through a source follower transistor that has its gate connected to a regulated DC voltage. The source follower transistor operates in the saturation region.

US Patent:

6741102, May 25, 2004

Filed:

Apr 26, 1999

Appl. No.:

09/300757

Inventors:

Thomas P. Thomas - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 7089

US Classification:

327 3, 327 12

Abstract:

Briefly, in accordance with one embodiment, an integrated circuit includes a phase-frequency detector (PFD) including two clock input ports, an up signal port and a down signal port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up output signal pulse and a down output signal pulse based, at least in part, upon the magnitude of an amount of phase delay between two respective clock signal pulses applied to the two input ports. Of course, additional embodiments are also disclosed.

US Patent:

6754407, Jun 22, 2004

Filed:

May 30, 2002

Appl. No.:

10/158250

Inventors:

Kishore K. Chakravorty - San Jose CA
Johanna Swan - Scottsdale AZ
Brandon C. Barnett - Beaverton OR
Joseph F. Ahadian - Carlsbad CA
Thomas P. Thomas - Beaverton OR
Ian Young - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G02B 612

US Classification:

385 14, 385 32

Abstract:

A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structures in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.

US Patent:

6760801, Jul 6, 2004

Filed:

Mar 6, 2001

Appl. No.:

09/801028

Inventors:

Thomas P. Thomas - Hillsboro OR
Ian A. Young - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

710305, 710100, 375257, 375377

Abstract:

A multi-drop bus input/output method and apparatus is disclosed. The apparatus comprises a multi-drop bus that has termination ends. The multi-drop bus also has a characteristic impedance. The multi-drop bus can be used for communication between devices. Devices that are attached to a termination end of the bus drive data onto the bus at the characteristic impedance. Devices that are attached to the bus, but not the termination ends, drive data onto the bus at one-half of the characteristic impedance. An end device terminates to ground with the characteristic impedance, and middle devices have high impedance, when not driving data.

US Patent:

6856129, Feb 15, 2005

Filed:

Jul 9, 2002

Appl. No.:

10/190712

Inventors:

Thomas P. Thomas - Beaverton OR, US
Douglas N. Stunkard - Portland OR, US
Miriam R. Reshotko - Portland OR, US
Brandon C. Barnett - Beaverton OR, US
Ian A. Young - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R031/00

US Classification:

3241581, 324765, 324767

Abstract:

A measurement system is provided that includes a probe device having an integrated amplifier. The integrated amplifier may be a transimpedence amplifier that amplifies input current to an output voltage.

US Patent:

7049704, May 23, 2006

Filed:

May 6, 2004

Appl. No.:

10/840017

Inventors:

Kishore K. Chakravorty - San Jose CA, US
Johanna Swan - Scottsdale AZ, US
Brandon C. Barnett - Beaverton OR, US
Joseph F. Ahadian - Carlsbad CA, US
Thomas P. Thomas - Beaverton OR, US
Ian Young - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/40

US Classification:

257778, 257737

Abstract:

A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structure in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens directly attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.

US Patent:

7418163, Aug 26, 2008

Filed:

Mar 28, 2002

Appl. No.:

10/109313

Inventors:

Kishore K. Chakravorty - San Jose CA, US
Joseph F. Ahadian - Carlsbad CA, US
Johanna Swan - Scottsdale AZ, US
Thomas P. Thomas - Beaverton OR, US
Brandon C. Barnett - Beaverton OR, US
Ian Young - Portland OR, US

International Classification:

G02B 6/12

US Classification:

385 14, 385129, 385130

Abstract:

An integrated optoelectrical package for optoelectrical integrated circuits (ICs) is disclosed. The package includes a package substrate having contact receiving members on an upper surface. The contact receiving members are electrically connected to contacts on the lower surface. An optoelectronic receiver package and an optoelectronic transmitter package are each electrically mounted to respective first and second subsets of the contact receiving members. Input and output waveguide arrays are formed atop the substrate package and are optically coupled to the optoelectronic receiver package and the optoelectronic transmitter package, respectively. The contacts on the lower surface of the package substrate are designed to contact and engage the contact receiving members of a standard printed circuit board (PCB).

Address:

1924 Redbird Dr, Las Vegas, NV 89134

Phone:

2087889493

VIN:

WA1AM74L89D037044

Make:

AUDI

Model:

Q7

Year:

2009

Address:

1924 Redbird Dr, Las Vegas, NV 89134

VIN:

JA4MT31X87U005319

Make:

MITSUBISHI

Model:

OUTLANDER

Year:

2007