- Dallas TX, US Rohit BHAN - Plano TX, US Thomas VERMEER - Plano TX, US Norelis MEDINA - Richardson TX, US
International Classification:
G06F 1/3206 G06F 1/24
Abstract:
A system includes an adapter port and a control circuit coupled to the adapter port. The system also includes host hardware coupled to the control circuit. The control circuit is configured to reset the host hardware in response to detecting an adapter removal pattern at the adapter port.
Texas Instruments
Digital Design Engineer at Texas Instruments
Intel Corporation May 2008 - Aug 2008
Digital Verification Intern
Education:
University of Florida 2008 - 2010
Master of Science, Masters, Computer Engineering, Management
University of Florida 2003 - 2008
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Verilog Fpga Integrated Circuit Design Systemverilog Rtl Design Analog Semiconductors Digital Ncsim C Verilog Ams Mixed Signal Ic Design Rtl Verification Verification Formal Verification Cadence Virtuoso Embedded Systems Debugging Cadence Cadence Spectre Fpga Prototyping Asic Perl Cadence Encounter Cadence Icfb