Thomas H Webber

US Patent:

61417416, Oct 31, 2000

Filed:

Aug 29, 1996

Appl. No.:

8/705057

Inventors:

Curtis Priem - Fremont CA
Satyanarayana Nishtala - Cupertino CA
Michael G. Lavelle - Saratoga CA
Thomas Webber - Cambridge MA
Daniel E. Lenoski - San Jose CA
Peter A. Mehring - Sunnyvale CA
Guy Moffat - Mountain View CA
Christopher R. Owen - Los Gatos CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1200

US Classification:

711217

Abstract:

A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

US Patent:

51365243, Aug 4, 1992

Filed:

Aug 3, 1990

Appl. No.:

7/562429

Inventors:

Curtis Priem - Fremont CA
Thomas Webber - Lynn MA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1564

US Classification:

395250

Abstract:

Circuitry for performing high speed operations on certain Boolean raster operations in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The circuitry includes a logic circuit for determining whether a particular Boolean raster operation is one for which the high speed operation is available. A Boolean raster operation is determined to be available for high speed operation if the outcome of the operation can be determined by reading only one operand, namely the source data. If the other operand, namely the destination data, is needed to determine the outcome if the operation, then the operation is performed normally. Otherwise, the operation may be performed by reading the source data only.

US Patent:

49581465, Sep 18, 1990

Filed:

Oct 14, 1988

Appl. No.:

7/257853

Inventors:

Curtis Priem - Fremont CA
Chris Malachowsky - Santa Clara CA
Thomas Webber - Lynn MA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G09G 540

US Classification:

340703

Abstract:

A mulitplexor implementation of circuitry for performing Boolean raster operation in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The invented circuitry includes a plane raster-op select circuit and Boolean raster-op circuit. The plane raster-op select circuit selects a Boolean raster operation to be performed for each plane of graphics information as a function of foreground and background color control signals. The selected Boolean raster operation for each plane is then input to set of mulitplexors and the selected Boolean raster operation is performed on the control inputs to the multiplexors which combines source and destination data for each plane according to the selected Boolean operation for that plane.