Thomas P Webber

US Patent:

6347348, Feb 12, 2002

Filed:

Jun 30, 1998

Appl. No.:

09/108918

Inventors:

Thomas P. Webber - Petersham MA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1314

US Classification:

710 52, 710 54, 710 56

Abstract:

A buffer management subsystem receives data from one or more source processes for transfer to one or more destination processes. The buffer management subsystem includes a buffer memory and a buffer pointer FIFO that associated with one of the destination process. The buffer pointer FIFO stores pointers to buffers in the buffer memory which are available to be used to store data from the source process(es) for transfer to the respective associated destination process. When data is received from a source process for transfer to a destination process, a buffer pointer is retrieved from the buffer pointer FIFO associated with the destination process and used in storing the data in the buffer pointed to by the buffer pointer. When the data is retrieved from the buffer for transfer to the destination process, the buffer pointer to the buffer is returned to the buffer pointer FIFO.

US Patent:

6529518, Mar 4, 2003

Filed:

Jun 11, 1998

Appl. No.:

09/096450

Inventors:

Thomas P. Webber - Petersham MA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04J 322

US Classification:

370403, 370258

Abstract:

A network adapter includes a bypass buffer with sufficient capacity to store a packet from an upstream neighboring adapter and to store at least one additional incoming packet as a local packet is sent. The adapter also includes control logic which monitors the bypass buffer to determine whether the adapter may send local data packets. A network may be formed of such network adapters linked through counterrotating rings. If the control logic determines that the bypass buffer has sufficient storage available to avoid overflow while the adapter sends the local packet, the adapter sends the local packet. The control logic may choose to send a local packet only if there is sufficient room available within the bypass buffer to store a packet the same size as the local packet which is to be sent, thereby insuring that the bypass buffer does not overflow before the adapter can resume transmitting data from the bypass buffer. If there is not sufficient room within the adapters bypass buffer, the adapter requests a pause in transmissions from its upstream neighbor which pause will permit the adapter to empty its bypass buffer and to then send a local packet. If the upstream neighbor cannot accommodate the pause request, it, in turn, requests a pause from its own upstream neighboring adapter, and so on, until a pause is effected and the original pause-requesting adapter can empty its bypass buffer and transmit its local packet.

US Patent:

6671690, Dec 30, 2003

Filed:

Apr 10, 2001

Appl. No.:

09/832681

Inventors:

Thomas Peter Webber - Petersham MA
Hugh Kurth - Lexington MA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1730

US Classification:

707100

Abstract:

Methods and apparatus for deleting a member in a circular singly linked list are described. Just prior to the current pointer register being updated, its contents are copied to the previous pointer register. When the consumer needs to delete a member from the list, the previous member location is known because it is saved in the previous pointer register. In this way, deletions done at the time of scanning involve only a single SRAM write access since the contents of the current pointer register is copied into the member referenced by the previous pointer register.

US Patent:

6744765, Jun 1, 2004

Filed:

Aug 24, 2000

Appl. No.:

09/645864

Inventors:

Glenn A. Dearth - Groton MA
Thomas P. Webber - Petersham MA
Kenneth A. Ward - Shrewsbury MA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 1228

US Classification:

370394, 370349, 370473, 370474, 709236, 709238, 714748, 714749

Abstract:

A method for transmitting messages between two processes includes creating a communications channel between a first channel adapter coupled to a client process and a second channel adapter coupled to a remote process. The method further includes reading a request message at the first channel adapter, segmenting the request message into a series of packets, assigning a sequence number to each packet, and transmitting the packets in order to the second channel adapter through the communications channel. The method further includes receiving the packets at the second channel adapter and sending at least one acknowledgement message to the first channel adapter in response to the received packets. The acknowledgement message has a packet sequence number field containing a packet sequence number and a payload containing a message sequence number, wherein the message sequence number identifies a complete message last received at the second channel adapter and the packet sequence number identifies a packet last received at the second channel adapter.

US Patent:

6820186, Nov 16, 2004

Filed:

Mar 26, 2001

Appl. No.:

09/817509

Inventors:

Thomas P. Webber - Petersham MA
Hugh Kurth - Lexington MA
Robert Dickson - Harvard MA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711219, 711121, 708209, 708700, 36518912, 36523008

Abstract:

Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer.

US Patent:

6857030, Feb 15, 2005

Filed:

Sep 12, 2001

Appl. No.:

09/949928

Inventors:

Thomas P. Webber - Petersham MA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F003/00
G06F013/14
G06F013/28

US Classification:

710 33, 710 5, 710 6, 710 35

Abstract:

A system and method for reducing the number of memory accesses by a hardware device to a descriptor memory is disclosed. Methods, systems and articles of manufacture consistent with the present invention enable software to embed a subsequent descriptor it is posting in the descriptor memory into a current descriptor listed in the descriptor memory. Additionally, hardware is configured to transmit a data packet associated with the current descriptor to a recipient device. When hardware receives an acknowledgment message from the recipient device associated with the transmitted data packet, it fetches the current descriptor to update a completion code within the current descriptor using a Read-Modify-Write (RMW) transfer sequence. As part of the RMW memory operation, hardware may use the embedded copy of the subsequent descriptor within the current descriptor to transmit the next data packet associated with the subsequent descriptor. This process avoids hardware from having to fetch the embedded descriptor from the descriptor memory before transmitting the next data packet.

US Patent:

6880057, Apr 12, 2005

Filed:

Jan 5, 2000

Appl. No.:

09/478140

Inventors:

Thomas P. Webber - Petersham MA, US
Ketan P. Joshi - Fremont CA, US

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F012/00

US Classification:

711169, 711168, 711154, 711201

Abstract:

A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively. By using a sideline buffer to temporarily store incomplete write instructions, processing of sequential memory access instructions can continue subject to observance of memory access conflict rules.

US Patent:

6883006, Apr 19, 2005

Filed:

Jun 25, 2001

Appl. No.:

09/891684

Inventors:

Thomas Peter Webber - Petersham MA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F017/30

US Classification:

707100, 707205

Abstract:

During a scan operation in a circular, singly linked list having a number of list entries each of which has an associated next pointer field and a root pointer register that includes a root pointer that points to, or otherwise references, an arbitrary list entry. In order to add a new list entry to the list, the root pointer included in the root pointer register is copied into a next pointer field of the added list entry. Next, the root pointer register is overwritten with a pointer that points to or otherwise references the added list entry. In this way, additions to a circular, singly linked list that are done at the time of scanning involve only a single SRAM write access.