Thomas Russell Webber

US Patent:

55398944, Jul 23, 1996

Filed:

Apr 20, 1993

Appl. No.:

8/049078

Inventors:

Thomas Webber - Cambridge MA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1206

US Classification:

395455

Abstract:

A sector cache tag structure for a computer system with a cache memory and a maximum amount of system memory is disclosed. Upon initial power-up of the computer system, the amount of system memory installed in the computer system is determined. A minimum number of sub-blocks for the cache memory is selected such that when less than the maximum amount of system memory is installed, fewer sub-blocks are selected for each block in the cache memory. Based on the optimal number of sub-blocks selected for the amount of installed memory, a plurality of cache tags, block valid bits and sub-block valid bits are stored. The number of cache tags and block valid bits is equivalent to the number of blocks in the cache memory, and the number of sub-block valid bits is equal to the number of sub-blocks. The cache tags are stored in a cache tag random access memory (RAM). The block valid bits are stored in a block valid RAM which is large enough to store all the block valid bits for a minimum amount of memory installed in the computer system, and the sub-block valid bits are stored in a sub-block valid RAM comprising a total size to support the maximum amount of memory installed.

US Patent:

51365243, Aug 4, 1992

Filed:

Aug 3, 1990

Appl. No.:

7/562429

Inventors:

Curtis Priem - Fremont CA
Thomas Webber - Lynn MA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1564

US Classification:

395250

Abstract:

Circuitry for performing high speed operations on certain Boolean raster operations in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The circuitry includes a logic circuit for determining whether a particular Boolean raster operation is one for which the high speed operation is available. A Boolean raster operation is determined to be available for high speed operation if the outcome of the operation can be determined by reading only one operand, namely the source data. If the other operand, namely the destination data, is needed to determine the outcome if the operation, then the operation is performed normally. Otherwise, the operation may be performed by reading the source data only.

US Patent:

49581465, Sep 18, 1990

Filed:

Oct 14, 1988

Appl. No.:

7/257853

Inventors:

Curtis Priem - Fremont CA
Chris Malachowsky - Santa Clara CA
Thomas Webber - Lynn MA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G09G 540

US Classification:

340703

Abstract:

A mulitplexor implementation of circuitry for performing Boolean raster operation in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The invented circuitry includes a plane raster-op select circuit and Boolean raster-op circuit. The plane raster-op select circuit selects a Boolean raster operation to be performed for each plane of graphics information as a function of foreground and background color control signals. The selected Boolean raster operation for each plane is then input to set of mulitplexors and the selected Boolean raster operation is performed on the control inputs to the multiplexors which combines source and destination data for each plane according to the selected Boolean operation for that plane.

US Patent:

49087800, Mar 13, 1990

Filed:

Oct 14, 1988

Appl. No.:

7/258133

Inventors:

Curtis Priem - Freemont CA
Thomas Webber - Lynn MA
Chris Malachowsky - Santa Clara CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1562
G09G 116

US Classification:

364521

Abstract:

A method and apparatus for performing anti-aliasing of rendered lines, text and images displayed by a workstation on a video display. The anti-aliasing is performed by logically dividing each addressable frame buffer pixel into sixteen sub-pixels and generating a gray scale value for the displayed pixel that is a function of the number of sub-pixels crossed by a portion of a rendered image. The invented circuitry is part of the circuitry used for combining source and destination data which forms the displayed image namely, an anti-aliasing mask and filter, adder/subtractor logic, saturation logic and anti-aliasing logic.