Thomas E Webber

US Patent:

6744765, Jun 1, 2004

Filed:

Aug 24, 2000

Appl. No.:

09/645864

Inventors:

Glenn A. Dearth - Groton MA
Thomas P. Webber - Petersham MA
Kenneth A. Ward - Shrewsbury MA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 1228

US Classification:

370394, 370349, 370473, 370474, 709236, 709238, 714748, 714749

Abstract:

A method for transmitting messages between two processes includes creating a communications channel between a first channel adapter coupled to a client process and a second channel adapter coupled to a remote process. The method further includes reading a request message at the first channel adapter, segmenting the request message into a series of packets, assigning a sequence number to each packet, and transmitting the packets in order to the second channel adapter through the communications channel. The method further includes receiving the packets at the second channel adapter and sending at least one acknowledgement message to the first channel adapter in response to the received packets. The acknowledgement message has a packet sequence number field containing a packet sequence number and a payload containing a message sequence number, wherein the message sequence number identifies a complete message last received at the second channel adapter and the packet sequence number identifies a packet last received at the second channel adapter.

US Patent:

7099345, Aug 29, 2006

Filed:

Nov 27, 2001

Appl. No.:

09/995356

Inventors:

Robert A. Dickson - Harvard MA, US
Farroukh Touserkani - Acton MA, US
Thomas P. Webber - Petersham MA, US
Hugh Kurth - Lexington MA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 12/54
H04L 12/28

US Classification:

370429, 370352, 37039572, 710 27, 711219

Abstract:

Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.

US Patent:

56870795, Nov 11, 1997

Filed:

Jun 1, 1995

Appl. No.:

8/457555

Inventors:

Robert M. Bauer - Shirley MA
Thomas P. Webber - Cambridge MA

Assignee:

Sun Microsystems, Inc. - Mountainview CA

International Classification:

H05K 720

US Classification:

364175

Abstract:

A computer has an AC power outlet, preferably a standard AC outlet, into which periperhal devices, such as video monitors, can be plugged. It can turn this outlet on and off under program control, preferably by writing an outlet control signal to an I/O port which controls the outlet. A activity monitor, preferably in software, generates outlet control signals when one or more of the computer's peripheral devices have been inactive for more than a predetermined time. In some embodiments, the activity monitor turn off different parts of the computer in response to different types of inactivity. Preferably the computer can turn off the AC outlet without turning off the computer as a whole, and preferably it turns off the AC power outlet when the computer is turned off. Normally the AC outlet and its switching circuitry are part of the computer's power supply. The invention also includes a computer which has one or more electrically powered fans and an I/O port to which its can write to produce different fan speed control signals.

US Patent:

55398944, Jul 23, 1996

Filed:

Apr 20, 1993

Appl. No.:

8/049078

Inventors:

Thomas Webber - Cambridge MA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1206

US Classification:

395455

Abstract:

A sector cache tag structure for a computer system with a cache memory and a maximum amount of system memory is disclosed. Upon initial power-up of the computer system, the amount of system memory installed in the computer system is determined. A minimum number of sub-blocks for the cache memory is selected such that when less than the maximum amount of system memory is installed, fewer sub-blocks are selected for each block in the cache memory. Based on the optimal number of sub-blocks selected for the amount of installed memory, a plurality of cache tags, block valid bits and sub-block valid bits are stored. The number of cache tags and block valid bits is equivalent to the number of blocks in the cache memory, and the number of sub-block valid bits is equal to the number of sub-blocks. The cache tags are stored in a cache tag random access memory (RAM). The block valid bits are stored in a block valid RAM which is large enough to store all the block valid bits for a minimum amount of memory installed in the computer system, and the sub-block valid bits are stored in a sub-block valid RAM comprising a total size to support the maximum amount of memory installed.