Thomas Garth Workman

US Patent:

7091063, Aug 15, 2006

Filed:

Feb 9, 2004

Appl. No.:

10/775890

Inventors:

Biswajit Sur - San Jose CA, US
Nagesh Vodrahalli - Phoenix AZ, US
Thomas Workman - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438118, 438106, 438119, 438121, 438122, 438612, 438613

Abstract:

To accommodate high power densities associated with high performance integrated circuits, heat is dissipated from a surface of a die through a solderable thermal interface to a lid or integrated heat spreader. In one embodiment, the die is mounted on an organic substrate using a C4 and land grid array arrangement. In order to maximize thermal dissipation from the die while minimizing warpage of the package when subjected to heat, due to the difference in thermal coefficients of expansion between the die and the organic substrate, a thermal interface is used that has a relatively low melting point in addition to a relatively high thermal conductivity. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.

US Patent:

20140079884, Mar 20, 2014

Filed:

Sep 12, 2013

Appl. No.:

14/024649

Inventors:

J. Wallace Parce - Palo Alto CA, US
Melissa Fardy - Belmont CA, US
Siglinde Schmid - San Jose CA, US
Thomas Workman - San Jose CA, US
Thomas Fong - San Francisco CA, US
William E. Jarvis - Millbrae CA, US
Benjamin Wang - Mountain View CA, US

Assignee:

Svaya Nanotechnologies, Inc - Sunnyvale CA

International Classification:

B05D 1/02

US Classification:

427352, 524430, 118313

Abstract:

The disclosure provides materials, apparatuses, and methods for making multilayer coatings with a high degree of efficiency and control. In some aspects, for example, coatings are described having multiple layers of nanoparticles and a polyelectrolyte, wherein the nanoparticles form tightly packed monolayers. The interface between monolayers may include polyelectrolyte material. One or more aspects of such monolayers and interfaces are controllable.

US Patent:

6724078, Apr 20, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/652430

Inventors:

Biswajit Sur - San Jose CA
Nagesh Vodrahalli - Phoenix AZ
Thomas Workman - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2312

US Classification:

257704, 257706, 257707, 257720, 257675, 257779, 257783, 438122, 438125, 438612, 438118

Abstract:

To accommodate high power densities associated with high performance integrated circuits, heat is dissipated from a surface of a die through a solderable thermal interface to a lid or integrated heat spreader. In one embodiment, the die is mounted on an organic substrate using a C4 and land grid array arrangement. In order to maximize thermal dissipation from the die while minimizing warpage of the package when subjected to heat, due to the difference in thermal coefficients of expansion between the die and the organic substrate, a thermal interface is used that has a relatively low melting point in addition to a relatively high thermal conductivity. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.

US Patent:

20220320035, Oct 6, 2022

Filed:

Mar 30, 2022

Appl. No.:

17/657332

Inventors:

- San Jose CA, US
Thomas Workman - San Jose CA, US

International Classification:

H01L 23/00

Abstract:

Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

US Patent:

20220293567, Sep 15, 2022

Filed:

Feb 25, 2022

Appl. No.:

17/681563

Inventors:

- San Jose CA, US
Rajesh Katkar - Milpitas CA, US
Thomas Workman - San Jose CA, US
Guilian Gao - San Jose CA, US
Laura Wills Mirkarimi - Sunol CA, US
Belgacem Haba - Saratoga CA, US
Gabriel Z. Guevara - San Jose CA, US
Joy Watanabe - Campbell CA, US

International Classification:

H01L 25/065
H01L 23/00
H01L 23/31
H01L 21/56

Abstract:

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

US Patent:

20230115122, Apr 13, 2023

Filed:

Sep 13, 2022

Appl. No.:

17/931826

Inventors:

- San Jose CA, US
Thomas Workman - San Jose CA, US
Gabriel Z. Guevara - San Jose CA, US
Dominik Suwito - San Jose CA, US
Guilian Gao - San Jose CA, US

International Classification:

H01L 21/762
H01L 21/786
H01L 21/321
H01L 21/02

Abstract:

Methods of bonding thin dies to substrates. In one such method, a wafer is attached to a support layer. The wafer and support layer are attached to a dicing structure and then singulated to form a plurality of semiconductor die components. Each semiconductor die component comprises a thinned die and a support layer section attached to the thinned die where each support layer section is disposed between the corresponding thinned die and the dicing structure. At least one of the semiconductor die components is then bonded to a substrate without an intervening adhesive such that the thinned die is disposed between the substrate and the support layer section. The support layer section is then removed from the thinned die.

US Patent:

20210098412, Apr 1, 2021

Filed:

May 14, 2020

Appl. No.:

16/874527

Inventors:

- San Jose CA, US
Laura Wills Mirkarimi - Sunol CA, US
Javier A. DeLaCruz - San Jose CA, US
Rajesh Katkar - Milpitas CA, US
Cyprian Emeka Uzoh - San Jose CA, US
Guilian Gao - San Jose CA, US
Thomas Workman - San Jose CA, US

International Classification:

H01L 23/00
H01L 23/31

Abstract:

A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.

US Patent:

20200411483, Dec 31, 2020

Filed:

Jun 24, 2020

Appl. No.:

16/911360

Inventors:

- San Jose CA, US
Rajesh Katkar - Milpitas CA, US
Thomas Workman - San Jose CA, US
Guilian Gao - San Jose CA, US
Laura Wills Mirkarimi - Sunol CA, US
Belgacem Haba - Saratoga CA, US
Gabriel Z. Guevara - Gilroy CA, US
Joy Watanabe - Campbell CA, US

International Classification:

H01L 25/065
H01L 23/00
H01L 23/31
H01L 21/56

Abstract:

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.