Timir N Raithatha

US Patent:

20120013406, Jan 19, 2012

Filed:

Jul 19, 2010

Appl. No.:

12/838719

Inventors:

Dan ZHU - High Point NC, US
Reuben Pascal Nelson - Colfax NC, US
Timir Raithatha - Greensboro NC, US
Wyn Palmer - Greensboro NC, US
John Cavey - Oak Ridge NC, US
Ziwei Zheng - Greensboro NC, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03L 7/00
H03B 19/00

US Classification:

331 34, 327117

Abstract:

A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word. The first frequency divider may have an input for a clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the input clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM. The system clock also may include a second frequency divider coupled to the DCO output clock signal outputting the feedback signal to the DPFD.