Timothy Mark Archer

US Patent:

6821407, Nov 23, 2004

Filed:

Aug 27, 2002

Appl. No.:

10/231147

Inventors:

Jonathan D. Reid - Sherwood OR
Timothy Mark Archer - Lake Oswego OR
Thomas Tan Vu - San Jose CA
Seshasayee Varadarajan - Wilsonville OR
Jon Henri - West Linn OR
Steven T. Mayer - Lake Oswego OR
David Sauer - Tigard OR
Anita Kang - Portland OR
Gerald Feldewerth - Beaverton OR

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25D 338

US Classification:

205292, 204252, 204282, 204237, 204238

Abstract:

An electroplating system includes (a) a phosphorized anode having an average grain size of at least about 50 micrometers and (b) plating apparatus that separates the anode from the cathode and prevents most particles generated at the anode from passing to the cathode. The separation may be accomplished by interposing a microporous chemical transport barrier between the anode and cathode. The relatively few particles that are generated at the large grain phosphorized copper anode are prevented from passing into the cathode (wafer) chamber area and thereby causing a defect in the part.

US Patent:

6909190, Jun 21, 2005

Filed:

Feb 16, 2001

Appl. No.:

09/788105

Inventors:

Jay E. Uglow - Livermore CA, US
Nicolas J. Bright - San Jose CA, US
Dave J. Hemker - San Jose CA, US
Kenneth P. MacWilliams - Monte Sereno CA, US
Jeffrey C. Benzing - Saratoga CA, US
Timothy M. Archer - Portland OR, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L023/48

US Classification:

257759, 257758, 257774

Abstract:

A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

US Patent:

7060605, Jun 13, 2006

Filed:

Feb 16, 2001

Appl. No.:

09/785999

Inventors:

Jay E. Uglow - Livermore CA, US
Nicolas J. Bright - San Jose CA, US
Dave J. Hemker - San Jose CA, US
Kenneth P. MacWilliams - Monte Sereno CA, US
Jeffrey C. Benzing - Saratoga CA, US
Timothy M. Archer - Portland OR, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/4763

US Classification:

438624

Abstract:

A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

US Patent:

7482247, Jan 27, 2009

Filed:

Sep 19, 2006

Appl. No.:

11/524502

Inventors:

George D. Papasouliotis - North Andover MA, US
Raihan M. Tarafdar - San Jose CA, US
Dennis M. Hausmann - Lake Oswego OR, US
Jeff Tobin - Mountain View CA, US
Adrianne K. Tipton - Pleasanton CA, US
Bunsen Nie - Fremont CA, US
Brian G. Lu - Fremont CA, US
Timothy M. Archer - Lake Oswego OR, US
Sasson Roger Somekh - Los Altos Hills CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/311

US Classification:

438437, 438789, 257E21245, 257E21546

Abstract:

Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0. 13 micron, for example 0. 1 micron or less) gaps with significantly reduced incidence of voids or weak spots involve the use of any suitable confirmal dielectric deposition technique and a dry etch back. The etch back part of the process involves a single step or an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality nanolaminate dielectric gap fill operations.

US Patent:

7501339, Mar 10, 2009

Filed:

Mar 23, 2006

Appl. No.:

11/389428

Inventors:

Jay E. Uglow - Livermore CA, US
Nicolas J. Bright - San Jose CA, US
Dave J. Hemker - San Jose CA, US
Kenneth P. MacWilliams - Monte Sereno CA, US
Jeffrey C. Benzing - Saratoga CA, US
Timothy M. Archer - Portland OR, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/4763

US Classification:

438623

Abstract:

A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

US Patent:

7799200, Sep 21, 2010

Filed:

Oct 5, 2006

Appl. No.:

11/544957

Inventors:

Steven T. Mayer - Lake Oswego OR, US
John Drewery - Santa Clara CA, US
Richard S. Hill - San Jose CA, US
Timothy Archer - Lake Oswego OR, US
Avishai Kepten - Lake Oswego OR, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25F 3/00
H01L 21/288
B23H 3/00

US Classification:

205640, 205123, 205666

Abstract:

Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.

US Patent:

7879218, Feb 1, 2011

Filed:

Dec 18, 2003

Appl. No.:

10/741048

Inventors:

Eric Webb - Salem OR, US
Jon Reid - Sherwood OR, US
Yuichi Takada - Tualatin OR, US
Timothy Archer - Lake Oswego OR, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25D 5/34

US Classification:

205210, 205296

Abstract:

The present invention provides improved methods and devices for electroplating copper on a wafer. Some implementations of the present invention involve the pre-treatment of the wafer with a solution containing accelerator molecules. Preferably, the bath into which the wafer is subsequently placed for electroplating has a reduced concentration of accelerator molecules. The pre-treatment causes a reduction in roughness of the electroplated copper surface, particularly during the initial phases of copper growth.

US Patent:

8197662, Jun 12, 2012

Filed:

Dec 17, 2010

Appl. No.:

12/971367

Inventors:

Eric Webb - Tigard OR, US
Jonathan D. Reid - Sherwood OR, US
Yuichi Takada - Tualatin OR, US
Timothy Archer - Lake Oswego OR, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25D 5/34

US Classification:

205210, 205118

Abstract:

The present invention provides improved methods and devices for electroplating copper on a wafer. Some implementations of the present invention involve the pre-treatment of the wafer with a solution containing accelerator molecules. Preferably, the bath into which the wafer is subsequently placed for electroplating has a reduced concentration of accelerator molecules. The pre-treatment causes a reduction in roughness of the electroplated copper surface, particularly during the initial phases of copper growth.