Timothy David Elliott

US Patent:

6405306, Jun 11, 2002

Filed:

May 25, 2001

Appl. No.:

09/866078

Inventors:

Timothy A. Elliott - Austin TX
G. Glenn Henry - Austin TX

Assignee:

IP First LLC - Fremont CA

International Classification:

G06F 9302

US Classification:

712222, 712221

Abstract:

An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.

US Patent:

6754810, Jun 22, 2004

Filed:

Apr 10, 2002

Appl. No.:

10/120538

Inventors:

Timothy A. Elliott - Austin TX
G. Glenn Henry - Austin TX

Assignee:

I.P.-First, L.L.C. - Fremont CA

International Classification:

G06F 9315

US Classification:

712225, 712221, 712222

Abstract:

An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating point data, and integer data, in a variety of numerical formats. Data is moved in and out of the floating point register as integer data, and is converted into floating point format as needed. Separate processor instructions are provided for format conversion and data transfer to allow conversion and transfer operations to be separated.

US Patent:

6791564, Sep 14, 2004

Filed:

May 5, 2000

Appl. No.:

09/565834

Inventors:

Timothy A. Elliott - Austin TX
G. Glenn Henry - Austin TX

Assignee:

IPFirst, LLC - Fremont CA

International Classification:

G09G 502

US Classification:

345589, 345605

Abstract:

A mechanism for, and method of, clipping a red-green-blue (RGB) integer value to an n-bit maximum value and a processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a multiplexer having a first input that accepts n low-order bits of the RGB integer value and a select input that accepts at least one high-order bit of the RGB integer value and (2) an n-bit maximum value generator, coupled to a second input of the multiplexer, that provides the n-bit maximum value to the second input, an output of the multiplexer providing the n low-order bits when the at least one high order bit has a zero value and providing the n-bit maximum value when the at least one high order bit has a nonzero value.

US Patent:

7539876, May 26, 2009

Filed:

Apr 16, 2004

Appl. No.:

10/826632

Inventors:

G. Glenn Henry - Austin TX, US
Thomas A. Crispin - Austin TX, US
Timothy A. Elliott - Austin TX, US
Terry Parks - Austin TX, US

Assignee:

Via Technologies, Inc. - Taipei

International Classification:

H04L 9/06

US Classification:

713190, 380264

Abstract:

An apparatus and method for performing cryptographic operations. In one embodiment, an apparatus is provided for performing cryptographic operations. The apparatus includes fetch logic, keygen logic, and execution logic. The fetch logic is disposed within a microprocessor and receives cryptographic instruction single atomic cryptographic instruction as part of an instruction flow executing on the microprocessor. The cryptographic instruction single atomic cryptographic instruction prescribes one of the cryptographic operations, and also prescribes that a provided cryptographic key be expanded into a corresponding key schedule for employment during execution of the one of the cryptographic operations. The keygen logic is disposed within the microprocessor and is operatively coupled to the single atomic cryptographic instruction. The keygen logic directs the microprocessor to expand the provided cryptographic key into the corresponding key schedule.

US Patent:

7917568, Mar 29, 2011

Filed:

Jul 23, 2007

Appl. No.:

11/781754

Inventors:

G. Glenn Henry - Austin TX, US
Timothy A. Elliott - Austin TX, US
Terry Parks - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 7/38

US Classification:

708523

Abstract:

An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.

US Patent:

8495343, Jul 23, 2013

Filed:

Jun 4, 2010

Appl. No.:

12/793821

Inventors:

G. Glenn Henry - Austin TX, US
Gerard M. Col - Austin TX, US
Timothy A. Elliott - Austin TX, US
Rodney E. Hooker - Austin TX, US
Terry Parks - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 9/00

US Classification:

712222, 712220

Abstract:

A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

US Patent:

8635262, Jan 21, 2014

Filed:

Dec 3, 2010

Appl. No.:

12/960246

Inventors:

Timothy A. Elliott - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 7/533

US Classification:

708628

Abstract:

An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit is configured to partition the first operand into parts responsive to assertion of the carryless signal, where the parts are configured such that a Booth encoder selects first partial products corresponding to a second operand and is precluded from selection of second partial products corresponding to the second operand, and where the second partial products are results of implicit carry operations. The first partial products are exclusive-ORed together to yield a carryless multiplication result.

US Patent:

8645448, Feb 4, 2014

Filed:

Dec 3, 2010

Appl. No.:

12/960231

Inventors:

Timothy A. Elliott - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 7/00
G06F 7/38

US Classification:

708492, 708629

Abstract:

An apparatus having a carryless preformat unit, a Booth encoder, a compressor, a left shifter, and exclusive-OR logic. The carryless preformat unit receives a multiplier operand and partitions the multiplier operand into parts. The Booth encoder receives the parts and directs selection of first partial products of a multiplicand that do not reflect implicit carry operations. The compressor sums the first partial products via a configuration of carry save adders that generate sum bits and carry bits, where generation of the carry bits is disabled during execution of the carryless multiplication. The left shifter shifts bits of one or more outputs of the compressor. The exclusive-OR logic is coupled to the compressor and the left shifter, and is configured to execute an exclusive-OR function on the outputs to yield a carryless multiplication result.