Timothy O Kelly

US Patent:

61512575, Nov 21, 2000

Filed:

Jan 26, 1998

Appl. No.:

9/013482

Inventors:

Smith E. Jeffrey - Aloha OR
Timothy W. Kelly - Beaverton OR
Stephen W. Kiss - Banks OR
Keith M. Self - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

36518905

Abstract:

An electronic circuit die is presented including a plurality of first and second input/output (I/O) pad buffer cells. The first I/O pad buffer cells include at least a latch for latching data signals received at a pad in the cell. Adjacent ones of these first I/O pad buffer cells are conductively coupled together using conductive trace pins. The second I/O pad buffer cells include a pad that receives clocking signal which are supplied to the latches of the first I/O pad buffer cells. Accordingly, data signals received at the pads of the die are latched in the pad as opposed to the core logic of the die. One benefit of providing the latching of data signals in the pad is that conductive traces between the latches and the core logic need not be precisely matched, thus reducing cost. Also, the first I/O pad buffer cells can be similarly constructed, thus reducing the complexity and cost of manufacture for the die.

US Patent:

61782068, Jan 23, 2001

Filed:

Jan 26, 1998

Appl. No.:

9/013479

Inventors:

Timothy W. Kelly - Beaverton OR
Stephen S. Pawlowski - Beaverton OR
Keith M. Self - Aloha OR
Jeffrey E. Smith - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 2500

US Classification:

375257

Abstract:

A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e. g. , on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.