Timothy J Lewis

US Patent:

6920566, Jul 19, 2005

Filed:

Jul 12, 2002

Appl. No.:

10/194857

Inventors:

Timothy A. Lewis - El Dorado Hills CA, US

Assignee:

Phoenix Technologies Ltd. - Milpitas CA

International Classification:

G06F012/14

US Classification:

713194, 713193, 711163

Abstract:

Systems, methods and software that use a programmable lock bit that disables read access to a firmware ROM until the CPU is reset or enters into a secure CPU mode. The present invention provides for secure system firmware by preventing access to and reading of the contents of the firmware ROM.

US Patent:

7043729, May 9, 2006

Filed:

Aug 8, 2002

Appl. No.:

10/214909

Inventors:

Timothy A. Lewis - El Dorado Hills CA, US

Assignee:

Phoenix Technologies Ltd. - Milpitas CA

International Classification:

G06F 9/46

US Classification:

718103, 718107, 718108, 712244, 712245, 710260, 710261, 710262, 710263, 710264, 710265, 710266, 710267, 710268, 710269

Abstract:

Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

US Patent:

7917762, Mar 29, 2011

Filed:

Sep 28, 2006

Appl. No.:

11/529140

Inventors:

Timothy Andrew Lewis - El Dorado Hills CA, US
Timothy Joseph Markey - San Jose CA, US

Assignee:

Phoenix Technologies Ltd. - Milpitas CA

International Classification:

H04L 9/32

US Classification:

713176, 726 4, 726 10, 705 54, 713180

Abstract:

A device and method for providing a secure execution environment includes retrieving a boot loader, for example, from the memory of an electronic device or from a peripheral component. Next, a determination is made as to whether the boot loader is authorized to be executed on the corresponding electronic device. If the boot loader is authorized, then the boot loader code is executed. By only allowing execution of authorized boot loaders, security related breaches are substantially reduced or eliminated; thereby, enhancing device integrity.

US Patent:

7949874, May 24, 2011

Filed:

Sep 28, 2006

Appl. No.:

11/529141

Inventors:

Timothy Andrew Lewis - El Dorado Hills CA, US
Timothy Joseph Markey - San Jose CA, US

Assignee:

Phoenix Technologies Ltd. - Milpitas CA

International Classification:

G06F 21/00

US Classification:

713170, 713 2, 710 1, 710 62

Abstract:

A method for providing a secure firmware operating environment includes detecting the presence of a new component, for example, a peripheral device. Next, a determination is made as to whether the peripheral device includes an option read-only memory. Next, a determination is made as to whether the option read-only memory is authorized to be executed on the corresponding device. If the option read-only memory is authorized, the code contained within the option read-only memory is executed. By only allowing execution of peripheral devices or components including authorized option read-only memories, security related breaches are substantially reduced or eliminated; thereby, enhancing device integrity.

US Patent:

8490116, Jul 16, 2013

Filed:

Jul 25, 2011

Appl. No.:

13/190343

Inventors:

Timothy Andrew Lewis - El Dorado Hills CA, US

Assignee:

Phoenix Technologies Ltd. - Milpitas CA

International Classification:

G06F 3/00

US Classification:

719323

Abstract:

Techniques for supporting legacy VGA video using UEFI standard and extended UEFI graphics drivers. When an operating system that does not natively support the UEFI display protocols requires video services provided by firmware, the operating system communicates a request for video services to a generic video option ROM. The generic video option ROM notifies a generic video SMM driver of the request for video services. Such notification may be performed using a software system management interrupt (SMI). Upon notification, the generic video SMM driver notifies a third party UEFI video driver of the request for video services. The third party video driver provides the requested video services to the operating system. In this way, a third party UEFI graphics driver may support a wide variety of operating systems, even those that do not natively support the UEFI display protocols.

US Patent:

20020162052, Oct 31, 2002

Filed:

Apr 25, 2001

Appl. No.:

09/841864

Inventors:

Timothy Lewis - El Dorado Hills CA, US

International Classification:

G06F011/00

US Classification:

714/036000

Abstract:

Methods that detect a user's desire to enter a firmware recovery mode using one or more software-detectable buttons, such as power and/or sleep buttons, such as those on the front panel or keyboard of a computer system. An exemplary firmware recovery method comprises the steps of detecting the status of the one or more software-detectable buttons at power-on, distinguishing between the normal use of the selected button(s) and as a recovery button(s), and initiating firmware recovery. Upon initial power-on, system firmware detects the one or more software-detectable buttons held down for a predetermined time period, or that are sequentially held down, after which the one or more software-detectable buttons are released. The depressing and releasing action of the selected button(s) is used as an indicator to initiate the recovery mode. The present invention thus uses traditional buttons to initiate firmware recovery mode.

US Patent:

20030154392, Aug 14, 2003

Filed:

Feb 11, 2002

Appl. No.:

10/073616

Inventors:

Timothy Lewis - El Dorado Hills CA, US

International Classification:

G06F009/445

US Classification:

713/200000, 713/002000

Abstract:

A system, method and software that secures system firmware located in shadow RAM from unauthorized tampering. The present invention adds protection, either as a whole, or to individual portions of shadow RAM, using a configuration register in a memory controller (or other chip containing shadow RAM attribute control), or an external trapping chip, that traps accesses to a register or registers normally used to enable reading, writing and/or caching of the shadow RAM and generates an interrupt. Only resetting of the trapping chip unlocks the shadow RAM and allows modifications to reading, writing and/or caching of the shadow RAM area. Since trusted code gains control after reset, malicious or run-away programs cannot gain control while the shadow RAM is vulnerable. The entire shadow RAM area or individual shadow RAM areas may be controlled. The present invention permits use of code in the shadow RAM without fear of its alteration, raising reliability from run-away applications or malicious attack.

US Patent:

20030158988, Aug 21, 2003

Filed:

Feb 20, 2002

Appl. No.:

10/081840

Inventors:

Timothy Lewis - El Dorado Hills CA, US

International Classification:

G06F013/24

US Classification:

710/260000

Abstract:

A system, method and software that provides for improved system management interrupt (SMI) latency the present invention includes a real-time clock, and a register file containing one or more timing sensitive registers. An index and data register is provided for accessing the timing sensitive registers in the register file. An update-in-progress status bit determines a certain fixed period of time for which the timing-sensitive registers are valid. A retriggerable, fixed duration timer is triggered by reads of zero from the update-in-progress status bit. A latch is provided that is set if the timer is running when a system management interrupt is asserted and cleared when SMI is deasserted. A mechanism is provided for reading the output status of the latch. A timer is provided that is triggered by reading zero from a first register location. A status latch is provided for storing the status of the timer, which status is read using a status bit. SMI handling code is provided that reads the status latch, and if the status latch is zero, exits the SMI handling code, and if the status latch is non-zero, writes A to I/O location 0x70 of a second register location, reads I/O location 0x71 from a third register location, and if bit of the value read from the third register location is set, repeats the previous two steps until the value of bit is not set, and then exits the SMI handling code.