Timothy W Mcnamara

US Patent:

6629280, Sep 30, 2003

Filed:

Sep 25, 2000

Appl. No.:

09/669462

Inventors:

Timothy J. Koprowski - Newburgh NY
William V. Huott - Holmes NY
Timothy G. McNamara - Fishkill NY
Pradip Patel - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01B 3128

US Classification:

714733, 324763

Abstract:

An exemplary embodiment of the invention is a method and apparatus for delaying the start of an array built-in self-test (ABIST) until after the ABIST memory arrays have been started. The length of the delay is determined by the value in a programmable delay located on the integrated circuit. The initiation of the ABIST test is delayed by the time specified in the programmable delay.

US Patent:

6629281, Sep 30, 2003

Filed:

Sep 26, 2000

Appl. No.:

09/669917

Inventors:

Timothy G. McNamara - Fishkill NY
William V. Huott - Holmes NY
Timothy J. Koprowski - Newburgh NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 2900

US Classification:

714733, 714718, 324763

Abstract:

This invention describes a method and apparatus, contained within an integrated circuit, for isolating failure by precisely controlling the number of clocks applied during built-in self-test (BIST). A programmable clock counter, on the integrated circuit, stores a specified number of clock cycles and sends a signal to stop a BIST engine once the specified number of clock cycles have been generated. The intermediate results can then be mapped bit by bit in order to isolate the cause of failure.

US Patent:

6748565, Jun 8, 2004

Filed:

Oct 2, 2000

Appl. No.:

09/676828

Inventors:

Glenn E. Holmes - Wappingers Falls NY
Timothy G. McNamara - Fishkill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714731, 714700

Abstract:

An exemplary embodiment of the invention is a method and apparatus for configuring system cycle time in a data processing system with at least one master latch clock generating a master latch clock signal and at least one slave latch clock generating a slave latch clock signal. Timing errors are detected during system hardware testing. Adjustments to the system timing are calculated based on error for at least one of a master latch clock signal and a slave latch clock signal. The on-cycle edge of at least one of the master latch clock signal and slave latch clock signal is adjusted based on the calculations while maintaining a corresponding mid-cycle edge of at least one of the master latch clock signal and the slave latch clock signal.

US Patent:

6990076, Jan 24, 2006

Filed:

May 18, 1999

Appl. No.:

09/313261

Inventors:

Timothy G. McNamara - Fishkill NY, US
Bryan J. Robbins - Poughkeepsie NY, US
William R. Reohr - Bronx NY, US

International Classification:

H04J 15/00

US Classification:

370241, 714726

Abstract:

At least one swapper circuit is electrically connected to a bus between a plurality of entities sharing the bus. The swapper comprises a pair of series connected latches and a tristate circuits, one for each data direction, connected in parallel. The swapper acts as a revolving door, capturing data traveling from either side of the bus and shuffling the data to the other side without collision. A latch circuit is connected at either end of the bus for capturing data arriving from the other side. In addition, each of the drive entities is provided with a master/slave latched equipped with scan-in/scan-out ports, respectively, to enable testing of the circuit by allowing internal nodes of the circuit to be observed without requiring an external connection for each node accessed. In a VLSI arrangement, the scan-in/scan-out ports are connected together from a plurality of such circuits such that a variety of test patterns for various hardware configurations may be realized.

US Patent:

7129764, Oct 31, 2006

Filed:

Feb 11, 2005

Appl. No.:

11/056024

Inventors:

William V. Huott - Holmes NY, US
Timothy G. McNamara - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/04

US Classification:

327291, 327299

Abstract:

A system for locally generating a ratio clock from a global clock based on a global clock gate signal includes a staging unit, a pass gate, and a state machine. The state machine is electrically connected to an output of the staging unit and an input of the pass gate. The state machine includes state elements and associated logic. The associated logic is configured to allow said state elements to pass through a number of logic states for every same number of consecutive edges of the global clock when the associated logic is enabled. The number is a positive integer.

US Patent:

7319348, Jan 15, 2008

Filed:

Jan 27, 2006

Appl. No.:

11/341032

Inventors:

William V. Huott - Holmes NY, US
Charlie C. Hwang - Hopewell Junction NY, US
Timothy C. McNamara - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/04

US Classification:

327115, 327291

Abstract:

Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0. 5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

US Patent:

7355460, Apr 8, 2008

Filed:

Jan 27, 2006

Appl. No.:

11/341038

Inventors:

William V. Huott - Holmes NY, US
Charlie C. Hwang - Hopewell Junction NY, US
Timothy G. McNamara - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/04

US Classification:

327115, 327291

Abstract:

A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0. 5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

US Patent:

7368958, May 6, 2008

Filed:

May 19, 2006

Appl. No.:

11/419224

Inventors:

William V. Huott - Holmes NY, US
Charlie C. Hwang - Hopewell Junction NY, US
Timothy G. McNamara - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 21/00

US Classification:

327115, 327117, 327291, 377 48

Abstract:

A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0. 5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.