Timothy James O'Leary

US Patent:

8201137, Jun 12, 2012

Filed:

Mar 6, 2009

Appl. No.:

12/399855

Inventors:

Pranav Bhushan - San Jose CA, US
Chandrashekar L. Chetput - San Jose CA, US
Timothy Martin O'Leary - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716139, 716104, 716106, 716132, 716136, 716138, 703 13, 703 14

Abstract:

A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

US Patent:

8401828, Mar 19, 2013

Filed:

Jul 15, 2010

Appl. No.:

12/837406

Inventors:

Prabal K. Bhattacharya - Cupertino CA, US
Timothy Martin O'Leary - Cupertino CA, US
William Scott Cranston - Haverhill MA, US
Walter Hartong - Isen, DE

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 2, 703 14, 703 15, 716104

Abstract:

Systems and methods for simulating and verifying an analog mixed signal design provide an analog mixed signal testbench configured to verify analog parameters of the design. The testbench can include a mechanism to fetch a value of an analog object in an analog portion of a mixed signal design. The testbench mechanism can include an argument specifying the name of the object and the analog quantity to be fetched for that object. The testbench can retrieve estimated values and can further specify timing constraints specifying absolute times or events at which values are to be measured and returned.

US Patent:

8578322, Nov 5, 2013

Filed:

Apr 4, 2012

Appl. No.:

13/439469

Inventors:

Pranav Bhushan - San Jose CA, US
Chandrashekar L. Chetput - San Jose CA, US
Timothy Martin O'Leary - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716139, 716100, 716105, 716106, 716110, 716111, 716124, 716132, 716136

Abstract:

A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

US Patent:

8601412, Dec 3, 2013

Filed:

Nov 18, 2011

Appl. No.:

13/300388

Inventors:

Donald J. O'Riordan - Sunnyvale CA, US
Prabal Kanti Bhattacharya - Cupertino CA, US
Timothy Martin O'Leary - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716103, 716101, 716102

Abstract:

A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.

US Patent:

20120198405, Aug 2, 2012

Filed:

Apr 4, 2012

Appl. No.:

13/439583

Inventors:

Pranav Bhushan - San Jose CA, US
Chandrashekar L. Chetput - San Jose CA, US
Timothy Martin O'Leary - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716112

Abstract:

A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.