Timothy J Patterson

US Patent:

6571468, Jun 3, 2003

Filed:

Feb 26, 2001

Appl. No.:

09/793288

Inventors:

Timothy Patterson - Costa Mesa CA
John Burke - Corona CA

Assignee:

Saturn Electronics Engineering, Inc. - Auburn Hills MI

International Classification:

H01K 310

US Classification:

29852, 174257, 174202, 361820, 427 96, 427 97

Abstract:

A method for forming a fine-pitch flip chip assembly interconnects fine pitch devices after they have been connected to a carrier substrate. A die having a plurality of conductive sections, such as solder balls, is attached to a conductive layer of the substrate. An interconnect pattern is then formed in the conductive layer to connect the conductive sections and generate electronic functionality to the assembly. By forming the interconnect pattern after the device have been connected to the carrier, the invention provides precise alignment between the devices and the interconnect pattern without actually aligning the two components during the assembly process.

US Patent:

6648213, Nov 18, 2003

Filed:

Mar 5, 2001

Appl. No.:

09/799280

Inventors:

Timothy Patterson - Costa Mesa CA
Alex Lim Tiang Hock - Singapore, SG

Assignee:

Saturn Electronics Engineering, Inc. - Auburn Hills MI

International Classification:

H01L 2144

US Classification:

228223, 22818022, 438107

Abstract:

A method for manufacturing a chip assembly includes the steps of applying a controlled amount of flux to a plurality of solder balls on a die, applying a non-fluxing underfill material to a substrate, and assembling the die and substrate together to form the chip assembly such that the non-fluxing underfill material is trapped in between the die and the substrate. By applying the underfill material to the substrate before the chip is assembled rather than afterward, the inventive method increases chip assembly speed while maintaining control over flux application to prevent the solder balls from collapsing, eliminate the need for a defined solder resist window, and maintain a consistent die-to-substrate clearance at the solder joint.

US Patent:

6846701, Jan 25, 2005

Filed:

Apr 11, 2003

Appl. No.:

10/411981

Inventors:

Timothy Patterson - Costa Mesa CA, US

Assignee:

Saturn Electronics & Engineering, Inc. - Auburn Hills MI

International Classification:

H01L 2144
H01L 2148
H01L 2150

US Classification:

438108, 438613, 438614, 438615, 257737, 257738

Abstract:

A method for forming a fine-pitch flip chip assembly interconnects fine pitch devices after they have been connected to a carrier substrate. A die having a plurality of conductive sections, such as solder balls, is attached to a conductive layer of the substrate. An interconnect pattern is then formed in the conductive layer to connect the conductive sections and generate electronic functionality to the assembly. By forming the interconnect pattern after the device have been connected to the carrier, the invention provides precise alignment between the devices and the interconnect pattern without actually aligning the two components during the assembly process.

US Patent:

20120273559, Nov 1, 2012

Filed:

Apr 27, 2012

Appl. No.:

13/457670

Inventors:

Timothy P. Patterson - Mission Viejo CA, US
William Lutap - Tustin CA, US
Roger Nguyen - Irvine CA, US

International Classification:

B23K 31/02
B23K 3/08

US Classification:

228221, 228 33, 228 8, 228218

Abstract:

A soldering device and method of soldering are disclosed. The device may include at least one soldering pallet assembly. The pallet assembly may be subjected to a first atmosphere configured within the soldering pallet assembly and a second atmosphere configured external to the pallet assembly, the second atmosphere is an ambient atmosphere. At least one solder element may be positioned within the first atmosphere, and the solder element may be configured to attach an electrical component to an integrated circuit chip that is positioned within the pallet assembly.

US Patent:

20130075850, Mar 28, 2013

Filed:

Aug 20, 2012

Appl. No.:

13/589676

Inventors:

Timothy Patrick Patterson - Mission Viejo CA, US
Tim J. Moran - Sunnyvale CA, US
Craig W. Forrest - Mission Viejo CA, US

International Classification:

H01L 31/0232
H01L 31/024
H01L 27/146

US Classification:

257432

Abstract:

An image sensor includes an imager die, a circuit board, and an optical layer. The circuit board is flip-chip bonded to the imager die. The optical layer is adhered to the circuit board and includes a first portion configured to refract light differently than a second portion. Both the first portion and the second portion are integrally formed with the optical layer.

US Patent:

51472104, Sep 15, 1992

Filed:

Oct 1, 1991

Appl. No.:

7/769475

Inventors:

Timothy P. Patterson - Costa Mesa CA
Carl E. Hoge - Encinitas CA

Assignee:

Western Digital Corporation - Irvine CA

International Classification:

H01R 909

US Classification:

439 91

Abstract:

A polymer film interconnect forms an electrical interconnect between a first pattern of electrical conductors on a first electrical component and a second pattern of electrical conductors on a second electrical component. The polymer film interconnect includes a thin, flexible, self-supporting dielectric polymeric film having a pattern of spaced apart thru-holes containing separate quantities of an electrically conductive bonding material capable of heat bonding to the first electrical conductors adjacent the first surface of the film and to the second conductors adjacent the second surface of the film. This provides a plurality of discrete electrically isolated conductive paths from the first pattern of electrical conductors through the film to the second pattern of electrical conductors on the opposite side of the film. The polymer film interconnect can be used for forming interconnects between a number of electrical components, including connections between an IC chip and a leadframe or spreader; an IC chip and a chip carrier; an IC chip and a circuit board; an IC chip carrier and a circuit board; and a spreader or leadframe and a circuit board.

US Patent:

52137155, May 25, 1993

Filed:

Apr 17, 1989

Appl. No.:

7/338954

Inventors:

Timothy P. Patterson - Costa Mesa CA
Carl E. Hoge - Encinitas CA

Assignee:

Western Digital Corporation - Irvine CA

International Classification:

H01B 106

US Classification:

252518

Abstract:

A directionally conductive polymer (DCP) provides an electrical interconnect between terminal or conductors on a pair of electrical components. The DCP is applied in viscous film form to the interface between the two components. The DCP comprises a resinous matrix containing metal particles in an amount normally causing the film to act as an electrical insulator. Electrical conduction through the film is normally inhibited in an unstressed state. When a stress is applied to the film, the metal particles make contact to form a continuous electrical path through the film in alignment with the applied stress. The metal particles maintain electrical insulating properties in regions of the film not subjected to the applied stress. In one embodiment, the film includes a metal polymer dispersed in a dielectric carrier resin. A first resinous material dissolved in a solvent contains a dispersion of metal particles.

US Patent:

50696262, Dec 3, 1991

Filed:

Aug 20, 1990

Appl. No.:

7/569518

Inventors:

Timothy P. Patterson - Costa Mesa CA
Carl E. Hoge - Encinitas CA
Joseph Baia - Santa Ana CA

Assignee:

Western Digital Corporation - Irvine CA

International Classification:

H01R 909

US Classification:

439 55

Abstract:

A plated plastic castellated interconnect comprises a substrate made from a molded polymeric material and having top and bottom surfaces with a plurality of separate mutually spaced apart castellations integrally molded to the substrate and projecting from the bottom surface of the substrate. A plurality of separate spaced apart recessed regions may be molded in an edge of the substrate and aligned with the castellations. A plurality of metal conductors are plated to the substrate as separate conductive circuit traces, so that each circuit trace extends continuously from the top surface, along the surface of a corresponding recess and to a common plane on a respective castellation at the bottom of the substrate. The plated metal castellations are arranged for soldering or gluing to contacts on a printed circuit board for electrical connection to an electrical component such as an IC chip connected to the circuit traces on the substrate. The plated plastic castellations on one component provide high lead pitch densities, complex configurations, and compliancy of electrical connections to a second electrical component, as well as other advantages.