Timothy M Platt

US Patent:

8051120, Nov 1, 2011

Filed:

Apr 10, 2008

Appl. No.:

12/100462

Inventors:

Timothy M. Platt - Williston VT, US
Richard Jean-Luc St-Pierre - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/10

US Classification:

708304, 708207, 708202, 708445

Abstract:

A circuit and design structure for a streaming digital data filter embodied in a machine readable medium, the design structure including: a data processing unit and a pointer processing unit, the data processing unit and the pointer unit connected to a control logic; the pointer processing unit consisting of n serially connected pointer processing stages from a first to a last pointer processing stage, each pointer processing stage except for the first and last processing stages of the pointer processing unit including a pointer register and a multiplexer, wherein n is a positive integer greater than 2; the data processing unit consisting of n serially connected data processing stages from a first data processing stage to a last data processing stage, each data processing stage including a multiplexer, a data register and a comparator; and one or more filter output stages connected to the data processing unit.

US Patent:

8171069, May 1, 2012

Filed:

Apr 10, 2008

Appl. No.:

12/100448

Inventors:

Timothy M. Platt - Williston VT, US
Richard Jean-Luc St-Pierre - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/10

US Classification:

708304

Abstract:

A method of filtering streaming digital data in real time. The method including: (a) initializing and storing a set of m data elements and an associated set of m pointer data from 1 to m in sequence, m an integer greater than 2; (b) receiving in real time a first or next data element of a digital data stream of sequential data elements; (c) simultaneously with (b), replacing a stored data element associated with the pointer datum m with the received data element, changing the pointer datum of m to 1, and incrementing the value of all other pointer data by 1; (d) simultaneously with (b) sorting in order from a low to high all stored data elements; (e) simultaneously with (b), maintaining the association of pointer datum and data elements; (f) simultaneously with (b), filtering all stored data elements; and (g) repeating (b) through (f) multiple times.

US Patent:

20040221252, Nov 4, 2004

Filed:

Apr 29, 2003

Appl. No.:

10/249661

Inventors:

Susan Lichtensteiger - Essex Junction VT, US
Phillip Normand - Williston VT, US
Timothy Platt - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50

US Classification:

716/006000

Abstract:

A method of analysis of an integrated circuit design having multiple voltage islands, including: (a) determining a clock path through the voltage islands; (b) determining a data path through the voltage islands; (c) determining which voltage islands are independent voltage islands; (d) determining which voltage islands are dependent voltage islands; (e) for the data path and the clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths; and (f) for the data path and the clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths.

US Patent:

20060247906, Nov 2, 2006

Filed:

Apr 27, 2005

Appl. No.:

10/908100

Inventors:

John Austin - Winooski VT, US
David Hathaway - Underhill VT, US
Timothy Platt - Williston VT, US
Stephen Wyatt - Jericho VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 17/50

US Classification:

703016000

Abstract:

A method in accordance with the invention for modeling period jitter for testing a modeled logic circuit. Clock signals can be derived from a phase lock loop having a voltage controlled oscillator for use to evaluate timing problems within a modeled circuit. An estimation of period jitter for the modeled clock signals can be made by considering the number of periods of the voltage controlled oscillator signal which generates the clock signal occurring within a test interval. By using the relationship as an index to a table, a value of period jitter may be obtained from a table which increases longer the timing interval being considered. Instructions for carrying out the steps of correcting intervals between clock signals used in static timing tests may be stored on a computer readable medium along with a table containing the amount of period jitter as a function of the number of VCO periods occurring within a testing period. The improved accuracy in period jitter estimation improves the reliability of static testing of modeled circuits.

US Patent:

20130226499, Aug 29, 2013

Filed:

Feb 29, 2012

Appl. No.:

13/407811

Inventors:

Timothy M. Platt - Williston VT, US
Mustapha Slamani - South Burlington VT, US
Tian Xia - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 19/00

US Classification:

702117

Abstract:

Disclosed are a testing system and method incorporating a test signal generator for generating a test signal with multiple tones uniformly distributed across a wideband having a specific bandwidth. This test signal is generated based on user-specified test signal parameter(s) (e.g., using an orthogonal frequency-division multiplexing (OFDM) spread spectrum technique) and processed (e.g., converted from digital to analog or shifted to a different wideband having the same bandwidth), as necessary, so that it is suitable for application to a specific device under test and so that the tones account for the full range of frequencies with the wideband operation of that device under test. After it is applied to the device under test, the resulting output signal is captured, processed (e.g., converted back to digital or shifted back to the initial wideband), as necessary, and analyzed in order to determine the frequency responses associated with each of the tones.

US Patent:

20200379585, Dec 3, 2020

Filed:

Jun 3, 2019

Appl. No.:

16/429702

Inventors:

- GRAND CAYMAN, KY
Kaushal KANNAN - Essex Junction VT, US
Ritin NAMBIAR - South Burlington VT, US
Timothy M. PLATT - Williston VT, US

International Classification:

G06F 3/041
G06F 3/0484
H04L 7/02

Abstract:

The present disclosure relates to a testing device and techniques of testing semiconductor structures and, more particularly, to an absolute phase measurement testing device and technique of testing semiconductor structures. The structure includes: a first frequency input source which provides a first signal to an up-converter at an input side of a test fixture; a down-converter on an output side of the test fixture; a second frequency signal source which provides a second signal at a higher frequency than the first signal to the up-converter and the down-converter on the output side of the test fixture; a bypass path which bypasses the test fixture and provides connection between the up-converter and the down-converter; and a digitizer that is connected to an output side of the down-converter.

US Patent:

20200049737, Feb 13, 2020

Filed:

Aug 10, 2018

Appl. No.:

16/100297

Inventors:

- Grand Cayman, KY
Hanyi Ding - Colchester VT, US
Timothy M. Platt - Williston VT, US

International Classification:

G01R 1/073
G01R 1/067

Abstract:

Embodiments of the disclosure provide a probe structured for electrical and photonics testing of a photonic integrated circuit (PIC) die, the probe including: a membrane having a first surface and an opposing second surface and including conductive traces, the membrane being configured for electrical coupling to a probe interface board (PIB); a set of probe tips positioned on the membrane, the set of probe tips being configured to send electrical test signals to the PIC die or receive electrical test signals from the PIC die; and a photonic test assembly disposed on the membrane and electrically coupled to the conductive traces of the membrane, the photonic test assembly positioned for substantial alignment with a photonic I/O element of the PIC die, wherein the photonic test assembly is configured to transmit a photonic input signal to the photonic I/O element or detect a photonic output signal from the photonic I/O element.