Timothy E Proch

US Patent:

6381659, Apr 30, 2002

Filed:

Jan 19, 1999

Appl. No.:

09/232764

Inventors:

Timothy Proch - Shrewsbury MA
Nick Horgan - Marlboro MA

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

G06F 1202

US Classification:

710 57, 710 36, 710 20, 710 21, 710 53, 710 52, 710 56, 711100, 711147, 711173, 703 13

Abstract:

A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between adjacent data blocks. The FIFO buffer has a read-pointer address register and a write-pointer address register and a bank of write-capture registers including at least a first pair and a second pair. The first pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a first data block written to the FIFO buffer register while the second pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a second data block written to the FIFO buffer. The first pair and second pair alternate in capturing and saving beginning and ending addresses of a plurality of data blocks written to the FIFO buffer. In reading data from the FIFO buffer, the read pointer address register is loaded with the previously saved write-pointer address associated with the beginning of each data block that is subsequently read.

US Patent:

6434664, Aug 13, 2002

Filed:

Feb 4, 1999

Appl. No.:

09/244723

Inventors:

Bruce Buch - Westboro MA
Nick Horgan - Marlboro MA
Justin J. Koller - Glendale CO
Diana Langer - Northborough MA
Timothy Proch - Shrewsbury MA

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

G06F 1200

US Classification:

711112, 711169

Abstract:

A non-volatile storage subsystem comprises a media I/O controller, a media access channel, and movable storage media. A non-volatile disk storage subsystem bas a read channel coupling a disk controller to a disk head assembly. A read channel interfacing subsystem is provided as part of the storage subsystem, and the read channel interfacing subsystem interfaces a disk controller to the read channel. The read channel interfacing subsystem comprises a set of process units and a pipeline manager.

US Patent:

60095423, Dec 28, 1999

Filed:

Mar 31, 1998

Appl. No.:

9/052813

Inventors:

Justin J. Koller - Westboro MA
Nick Horgan - Marlboro MA
Bruce Buch - Westboro MA
Diana Langer - Northborough MA
Timothy Proch - Shrewsbury MA

Assignee:

Quantum Corporation - Milpitas CA

International Classification:

G06F 1134

US Classification:

714 53

Abstract:

A method of data transfer in a data processing system having at least one source buffer and at least one destination buffer. The source buffer includes a plurality of data blocks, each data block having an address and being for storage of data including an identifier uniquely identifying that data block. The destination buffer includes a plurality of data blocks corresponding to the data blocks of the source buffer, each destination block having an address and being for storage of data. Each source block identifier is a function of a corresponding destination block address. Transferring data from the source buffer to the destination buffer includes: (a) obtaining the address of a data block in the destination buffer to transfer data into; (b) obtaining the address of a corresponding data block in the source buffer to transfer data from; and (c) checking the integrity of said addresses before data transfer, including: (i) retrieving the source block identifier in the source block via the source block address; (ii) generating an expected identifier value for the source block from the address of the destination block via said function relation between the source block identifier and the destination block address; (iii) comparing the expected identifier value with the retrieved identifier value; and (iv) if there is a mismatch, signaling an error condition representing corruption of one or more of the source block and the destination block addresses.