Timothy J Sullivan

US Patent:

6417572, Jul 9, 2002

Filed:

Jul 16, 1999

Appl. No.:

09/354592

Inventors:

Dureseti Chidambarrao - Weston CT
Ronald G. Filippi - Wappingers Falls NY
Robert Rosenberg - Cortlandt Manor NY
Thomas M. Shaw - Peekskill NY
Timothy D. Sullivan - Underhill VT
Richard A. Wachnik - Mount Kisco NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257773, 257775, 257765

Abstract:

A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.