Toan K Do

US Patent:

6985011, Jan 10, 2006

Filed:

Dec 16, 2003

Appl. No.:

10/738811

Inventors:

Toan D. Do - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/177

US Classification:

326 38, 326 41, 716 16

Abstract:

Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit positions. The method further includes reading a second configuration frame from a memory. The second configuration frame is related to the first configuration frame. The method further includes creating a third configuration frame by placing information from the second configuration frame into positions indicated by the first configuration frame. The method further includes configuring the PLD using the third configuration frame. In this manner, the second configuration frame may occupy less space in the memory, and may be read more quickly, than a frame that also included position information.

US Patent:

7085870, Aug 1, 2006

Filed:

Sep 7, 2004

Appl. No.:

10/936147

Inventors:

Toan D. Do - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1/00

US Classification:

710302

Abstract:

Integrated circuits such as programmable logic devices are provided with hotsocket detection circuitry. The hotsocket detection circuitry monitors signals on data pins and power supply voltages. If the data pins become active before the power supply voltages have reached appropriate levels, a hotsocket condition is identified. When a hotsocket condition is identified, driver circuitry on the integrated circuit can be disabled by a hotsocket signal. Conductive paths may be used to share hotsocket detectors among multiple blocks of input-output circuitry.

US Patent:

7411853, Aug 12, 2008

Filed:

Nov 17, 2005

Appl. No.:

11/282437

Inventors:

Lin-Shih Liu - Fremont CA, US
Mark T. Chan - San Jose CA, US
Toan D. Do - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 5/14

US Classification:

365226, 326 40, 365154, 36518511

Abstract:

Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

US Patent:

7884644, Feb 8, 2011

Filed:

Feb 21, 2010

Appl. No.:

12/709492

Inventors:

Luqiong Wu - San Jose CA, US
Linda Chu - San Jose CA, US
Toan D. Do - San Jose CA, US
Jack Chui - Fremont CA, US
Praveen Krishnanunni - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/094

US Classification:

326 68, 326 81

Abstract:

A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.

US Patent:

7893716, Feb 22, 2011

Filed:

May 11, 2007

Appl. No.:

11/801864

Inventors:

Jack Chui - Fremont CA, US
Toan D. Do - San Jose CA, US
Kok Siong Tee - Gelugor, MY

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/0175

US Classification:

326 82, 326 38, 326 81

Abstract:

Hotsocket detection circuitry is provided for detecting hotsocket conditions in integrated circuits such as programmable logic device integrated circuits. Power-on-reset circuitry may provide a power-on-reset signal that is indicative of when power supply voltages are ready to power circuitry on the integrated circuit for normal operation. A delay circuit that is powered by a power supply voltage may receive the power-on-reset signal and may generate a corresponding delayed version of the power-on-reset signal. The delayed version of the power-on-reset signal may be provided to the hotsocket detection circuitry to ensure that the hotsocket detection circuitry produces a hotsocket signal that transitions after a transition in the power-on-reset signal. The delay circuit may include one or more inverter stages.

US Patent:

8013632, Sep 6, 2011

Filed:

Dec 15, 2009

Appl. No.:

12/638799

Inventors:

Jack Chui - Fremont CA, US
Linda Chu - San Jose CA, US
Toan D. Do - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/0175

US Classification:

326 82, 326 81, 326 38

Abstract:

Integrated circuits such as programmable logic devices are provided with hotsocket detection circuitry. The hotsocket detection circuitry monitors signals on data pins and power supply voltages. If the data pins become active before the power supply voltages have reached appropriate levels, a hotsocket condition is identified. When a hotsocket condition is identified, driver circuitry on the integrated circuit can be disabled by a hotsocket signal. The integrated circuit may include multiple blocks of input-output circuitry, each of which includes a local hotsocket circuit that uses global hotsocket and power-on-reset signals in disabling input-output circuitry in that input-output block. A power supply circuit in each input-output block may ensure that the local hotsocket circuit in that input-output block is powered.

US Patent:

7363414, Apr 22, 2008

Filed:

Jun 9, 2006

Appl. No.:

11/450047

Inventors:

Toan D. Do - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 13/00

US Classification:

710302, 710304

Abstract:

Integrated circuits such as programmable logic devices are provided with hotsocket detection circuitry. The hotsocket detection circuitry monitors signals on data pins and power supply voltages. If the data pins become active before the power supply voltages have reached appropriate levels, a hotsocket condition is identified. When a hotsocket condition is identified, driver circuitry on the integrated circuit can be disabled by a hotsocket signal. Conductive paths may be used to share hotsocket detectors among multiple blocks of input-output circuitry.

US Patent:

7995375, Aug 9, 2011

Filed:

Jul 8, 2008

Appl. No.:

12/169598

Inventors:

Lin-Shih Liu - Fremont CA, US
Mark T. Chan - San Jose CA, US
Toan D. Do - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 11/00

US Classification:

365154, 365156, 365226

Abstract:

Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.