Todd Charles Martin

US Patent:

8259111, Sep 4, 2012

Filed:

Aug 4, 2008

Appl. No.:

12/185474

Inventors:

Vineet Goel - Winter Park FL, US
Todd Martin - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 15/50
G06T 15/10
G06T 1/20

US Classification:

345426, 345427, 345506

Abstract:

A method, computer program product, and system are provided for processing data in a graphics pipeline. An embodiment of the method includes processing one or more vertices of a geometric primitive with a vertex shader function and generating new primitive information for the one or more processed vertices with a geometry shader function. The geometry shader function receives one or more processed vertices from the vertex shader function and emits a single vertex associated with the new primitive information. Each emitted vertex from the geometry shader function can be stored in a memory device. Unlike conventional graphic pipelines that require a memory device for data storage during the vertex and geometry shading processes, the present invention increases efficiency in the graphics pipeline by eliminating the need to access memory when the vertex and geometry shaders process vertex information.

US Patent:

20110057938, Mar 10, 2011

Filed:

Sep 9, 2010

Appl. No.:

12/878667

Inventors:

Todd Martin - Orlando FL, US
Vineet Goel - Winter Park FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 15/80
G06F 9/302
G06F 9/305

US Classification:

345505, 712221, 712E09017, 712E09018

Abstract:

A system and method are presented by which data on a graphics processing unit (GPU) can be output to one or more buffers with independent output frequencies. In one embodiment, a GPU includes a shader processor configured to respectively emit a plurality of data sets into a plurality of streams in parallel. Each data is emitted into at least a portion of its respective stream. Also included is a first number of counters configured to respectively track the emitted data sets.

US Patent:

20120017062, Jan 19, 2012

Filed:

Jul 19, 2011

Appl. No.:

13/186038

Inventors:

Vineet GOEL - Winter Park FL, US
Todd Martin - Orlando FL, US
Mangesh Nijasure - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 15/76
G06F 9/06
G06F 12/02

US Classification:

711170, 712 30, 712E09003, 711E12002

Abstract:

Methods are disclosed for improving data processing performance in a processor using on-chip local memory in multiple processing units. According to an embodiment, a method of processing data elements in a processor using a plurality of processing units, includes: launching, in each of the processing units, a first wavefront having a first type of thread followed by a second wavefront having a second type of thread, where the first wavefront reads as input a portion of the data elements from an off-chip shared memory and generates a first output; writing the first output to an on-chip local memory of the respective processing unit; and writing to the on-chip local memory a second output generated by the second wavefront, where input to the second wavefront comprises a first plurality of data elements from the first output. Corresponding system and computer program product embodiments are also disclosed.

US Patent:

20120019541, Jan 26, 2012

Filed:

Jul 20, 2010

Appl. No.:

12/839965

Inventors:

Vineet Goel - Winter Park FL, US
Ralph C. Taylor - Deland FL, US
Todd E. Martin - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Synnyvale CA

International Classification:

G06F 15/80

US Classification:

345505

Abstract:

Disclosed herein is a vertex core. The vertex core includes a grouper module configured to process two or more primitives during one clock period and two or more vertex translators configured to respectively receive the two or more processed primitives in parallel.

US Patent:

20130162651, Jun 27, 2013

Filed:

Dec 23, 2011

Appl. No.:

13/336635

Inventors:

Todd Martin - Orlando FL, US
Mangesh Nijasure - Orlando FL, US
Vineet Goel - Winter Park FL, US
Jason David Carroll - Oviedo FL, US

International Classification:

G06T 11/20

US Classification:

345441

Abstract:

Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.

US Patent:

20130169634, Jul 4, 2013

Filed:

Apr 18, 2012

Appl. No.:

13/449410

Inventors:

Vineet GOEL - Winter Park FL, US
Jason David Carroll - Oviedo FL, US
Mangesh Nijasure - Orlando FL, US
Todd Martin - Orlando FL, US

International Classification:

G06T 17/20

US Classification:

345423

Abstract:

Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.

US Patent:

20130169635, Jul 4, 2013

Filed:

May 22, 2012

Appl. No.:

13/477808

Inventors:

Jason CARROLL - Oviedo FL, US
Vineet GOEL - Winter Park FL, US
Mangesh NIJASURE - Orlando FL, US
Todd E. MARTIN - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 11/20
G06T 17/20

US Classification:

345423, 345441

Abstract:

Disclosed herein is a vertex core. The vertex core includes a reset scanner configured to remove reset indices and partial primitives in an input stream and resolve draw calls into sub-draw calls at reset index boundaries; and provide the resolved sub-draw calls to a plurality of downstream vertex grouper tessellators.

US Patent:

20140078156, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/616474

Inventors:

Jason Carroll - Oviedo FL, US
Vineet Goel - Winter Park FL, US
Mangesh Nijasure - Orlando FL, US
Todd E. Martin - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 1/20

US Classification:

345505

Abstract:

A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.