Tom D Conte

US Patent:

20110153984, Jun 23, 2011

Filed:

Dec 21, 2009

Appl. No.:

12/642870

Inventors:

Andrew WOLFE - Los Gatos CA, US
Tom CONTE - Atlanta GA, US

International Classification:

G06F 15/76
G06F 9/30
G06F 1/26
G06F 1/04

US Classification:

712 42, 713300, 713600, 712E09016

Abstract:

Embodiments of the disclosure generally set forth techniques for supplying different voltage levels and clock signals to a processor core. One example method includes determining a first workload of a first processor core in the multi-core processor for performing a first computing task associated with a first image area and a first geometric mapping between the first computing task and the first processor core, selecting a first voltage level or a first clock signal having a first clock frequency for the first processor core based on the determined first workload, wherein the first voltage level is compatible with the selected first clock frequency, initiating a voltage change to the first processor core based on the selected first voltage level, and initiating a clock change to the first processor core based on the selected first clock signal having the first clock frequency.

US Patent:

20110154089, Jun 23, 2011

Filed:

Dec 21, 2009

Appl. No.:

12/642871

Inventors:

Andrew WOLFE - Los Gatos CA, US
Tom CONTE - Atlanta GA, US

International Classification:

G06F 1/06

US Classification:

713501

Abstract:

Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to calculating a clock rate for one or more of the processor cores in the multi-core processor. One example method may include determining a first estimated workload for a first processor core and a second estimated workload for a second processor core within a scheduling interval in a periodic scheduling environment. In addition, a first clock rate for the first processor core may be calculated based on one or more of the first estimated workload, a maximum clock rate supported by the multi-core processor and/or the scheduling interval. Similarly, a second clock rate for the second processor core may also be calculated based on one or more of the second estimated workload, the maximum clock rate, and/or the scheduling interval.

US Patent:

20110047351, Feb 24, 2011

Filed:

Aug 20, 2009

Appl. No.:

12/545063

Inventors:

Andrew WOLFE - Los Gatos CA, US
Tom CONTE - Atlanta GA, US

International Classification:

G06F 15/76
G06F 9/02

US Classification:

712 28, 712E09002

Abstract:

A network of switches may be adapted to route image data to one or more processor cores based on tags associated with data samples, where each tag includes at least one reference-space coordinate value. When image data is received by the network, the image data may be spatially transformed to a reference space, e.g., the physical space that is represented by the image data, to generate the data samples and each data sample may be tagged with a corresponding reference space coordinate value and routed through the network to one or more of the processors according to the tag.