Tom J Gustafson

US Patent:

7427874, Sep 23, 2008

Filed:

Dec 3, 2007

Appl. No.:

11/949454

Inventors:

Om P. Agrawal - Los Altos CA, US
Ravindar M. Lall - Portland OR, US
David L. Rutledge - Portland OR, US
Tom Gustafson - Portland OR, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/173

US Classification:

326 38, 326 41

Abstract:

A programmable logic device in accordance with an embodiment of the invention includes configurable logic blocks, embedded random access memory (RAM) blocks, and input/output blocks adapted to transfer information into or out of the programmable logic device. An interconnect architecture is adapted to route information among the configurable logic blocks, embedded RAM blocks, and input/output blocks within the programmable logic device. An interface block is provided that couples an embedded RAM block and an input/output block but not a logic block to the interconnect architecture.

US Patent:

7327159, Feb 5, 2008

Filed:

Nov 28, 2005

Appl. No.:

11/287720

Inventors:

Om P. Agrawal - Los Altos CA, US
Ravindar M. Lall - Portland OR, US
David L. Rutledge - Portland OR, US
Tom Gustafson - Portland OR, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/173

US Classification:

326 38, 326 41

Abstract:

In accordance with an embodiment of the present invention, a programmable logic device includes a memory adapted to store information in the programmable logic device, an input/output circuit adapted to transfer information into or out of the programmable logic device, and an interconnect architecture adapted to route information within the programmable logic device. An interface circuit is provided to couple the memory and the input/output circuit to the interconnect architecture.