Toru Baji

US Patent:

50918648, Feb 25, 1992

Filed:

Dec 21, 1989

Appl. No.:

7/455141

Inventors:

Toru Baji - Burlingame CA
Hidenori Inouchi - Donnybrook, IE

Assignee:

Hitachi, Ltd. - Tokyo

International Classification:

G06F 1518

US Classification:

395 27

Abstract:

A neural net signal processor provided with a single layer neural net constituted of N neuron circuits which sums the results of the multiplication of each of N input signals Xj(j=1 to N) by a coefficient mij to produce a multiply-accumulate value ##EQU1## thereof, in which input signals Xj(j=1 to N) for input to the single layer neural net are input as serial input data, comprising: a multiplicity of systolic processor elements SPE-1(i=1 to M), each comprised of a two-state input data delay latch; a coefficient memory; means for multiplying and summing for multiply-accumulate output operations; an accumulator; a multiplexor for selecting a preceding stage multiply-accumulate output Sk(k=1 to i-1) and the multiply-accumulate product Si computed by the said circuit; wherein the multiplicity of systolic processor elements are serially connected to form an element array and element multiply-accumulate output operations are executed sequentially to obtain the serial multiply-accumulate outputs Si(i=1 to M) of one layer from the element array.

US Patent:

52416798, Aug 31, 1993

Filed:

Jun 27, 1990

Appl. No.:

7/545290

Inventors:

Tetsuya Nakagawa - Millbrae CA
Masafumi Miyamoto - Koganei, JP
Yasuhiro Sagesaka - Kodaira, JP
Toru Baji - Burlingame CA

Assignee:

Hitachi Ltd. - Tokyo

International Classification:

G06F 1300

US Classification:

395725

Abstract:

A data processor comprises a plurality of registers 1 (registers a to d), a plurality of data saving stack memory devices 2 coupled to the registers 1 for exclusive use thereof, respectively, and an instruction decoder for decoding instructions for controlling the registers 1 and the data saving stack memory devices 2 in accordance with the result of the instruction decoding. In response to an instruction "PUSH", the contents of the registers 1 (registers a to d) are selectively saved to the data saving stack memory device 2. In response to a instruction "POP", the contents of the data saving stack memory devices 2 are selectively restored to the registers 1 (registers a to d). Each of the instructions "PUSH" and "POP" has a field for indicating need or needlessness of the saving and restoration for each of the registers 1 and each of the data saving memories 2.

US Patent:

55354173, Jul 9, 1996

Filed:

Sep 27, 1993

Appl. No.:

8/127429

Inventors:

Toru Baji - San Jose CA
Atsushi Kiuchi - Kunitachi, JP

Assignee:

Hitachi America, Inc. - Tarrytown NY

International Classification:

G06F 1328

US Classification:

395842

Abstract:

A single chip digital signal processor (DSP) includes memory mapped resources and an on-chip direct memory access controller (DMAC). The memory mapped resources of the DSP include an on-chip program memory, an on-chip data memory, internal registers and memory mapped external memories and peripheral devices. The DMAC includes a host computer interface that processes host originated data transfer commands for transferring data to and from memory mapped resources of the DSP, and commands for setting the mode of operation of the DSP. The DMAC also has a dedicated interrupt controller for handling interrupts from a host computer and from peripheral devices. The DMAC processes interrupts from the host while a primary direct memory access transfer is being performed by the DMAC without having to store address register and count register information in a memory stacking area. As a result, the DMAC can switch from a primary DMA transfer to a host data transfer and back without using any instruction cycles for "overhead" associated with storing and restoring registers in a memory stacking area. The DMAC's host interface is also designed to be connected to a byte-structured boot ROM and the DMAC includes a boot sequencer for automatically loading a boot program from the ROM into the DMAC's on-chip instruction memory whenever the DSP is reset and a boot ROM is connected to the host interface.

US Patent:

51631113, Nov 10, 1992

Filed:

Aug 14, 1990

Appl. No.:

7/567010

Inventors:

Toru Baji - Burlingame CA
Kouki Noguchi - Kokubunji, JP
Tetsuya Nakagawa - Millbrae CA
Motonobu Tonomura - Kodaira, JP
Hajime Akimoto - Mobara, JP
Toshiaki Masuhara - Tokyo, JP

Assignee:

Hitachi, Ltd. - Tokyo

International Classification:

G06F 1518

US Classification:

395 22

Abstract:

There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

US Patent:

55133746, Apr 30, 1996

Filed:

Sep 27, 1993

Appl. No.:

8/127685

Inventors:

Toru Baji - San Jose CA

Assignee:

Hitachi America, Inc. - Tarrytown NY

International Classification:

G06F 1328

US Classification:

395846

Abstract:

A single chip digital signal processor (DSP) includes memory mapped resources and an on-chip direct memory access controller (DMAC). The memory mapped resources of the DSP include an on-chip program memory, an on-chip data memory, internal registers and memory mapped external memories and peripheral devices. The DMAC includes separate address and count registers for handling a primary data transfer and two interrupt data transfers. The count registers share the same decrementer and the address registers share the same address computation circuit. The DMAC also has a dedicated interrupt controller for handling interrupts from a host computer and from peripheral devices. The DMAC processes interrupts from the host and two peripheral devices while a primary direct memory access transfer is being performed by the DMAC without having to store address register and count register information in a memory stacking area. As a result, the DMAC can switch from a primary DMA transfer to an interrupt DMA transfer or a host DMA transfer and back without using any instruction cycles for "overhead" associated with storing and restoring registers in a memory stacking area. The DMAC also includes a host computer interface that processes host originated data transfer commands for transferring data to and from memory mapped resources of the DSP, and commands for setting the mode of operation of the DSP.

US Patent:

57404046, Apr 14, 1998

Filed:

Sep 27, 1993

Appl. No.:

8/127682

Inventors:

Toru Baji - San Jose CA

Assignee:

Hitachi America Limited - Tarrytown NY

International Classification:

G06F 1200
G06F 1300
G06F 104

US Classification:

395494

Abstract:

A digital signal processor (DSP) provides an improvement in the interfacing and sharing of external memory devices. Specifically, the digital signal processor is provided with a parallel interface for communicating with external memory devices, a chip select decoder located on-chip for selectably enabling external memory devices, and a wait status controller for holding processor operation until the selected memory device is ready. The memory architecture is configurable for internal or external wait state generation and memory sharing with other DSPs so that a plurality of varying speed memory devices may be accessed. The chip select decoder includes a programmable register for storing a mode configuration word for defining a plurality of external memory configurations.

US Patent:

54267455, Jun 20, 1995

Filed:

Mar 3, 1994

Appl. No.:

8/206195

Inventors:

Toru Baji - Burlingame CA
Kouki Noguchi - Kokubunji, JP
Tetsuya Nakagawa - Millbrae CA
Motonobu Tonomura - Kodaira, JP
Hajime Akimoto - Mobara, JP
Toshiaki Masuhara - Tokyo, JP

Assignee:

Hitachi, Ltd. - Tokyo

International Classification:

G06F 1518

US Classification:

395375

Abstract:

There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

US Patent:

56385242, Jun 10, 1997

Filed:

May 17, 1995

Appl. No.:

8/443199

Inventors:

Atsushi Kiuchi - Kunitachi, JP
Toru Baji - San Jose CA
Tetsuya Nakagawa - Koganei, JP
Kenji Kaneko - Sagamihara, JP

Assignee:

Hitachi America, Ltd. - Tarrytown NY

International Classification:

G06F 930

US Classification:

395375

Abstract:

A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the instruction memory so as to select one instruction word in the instruction memory. Every DSP instruction word identifies one data processing operation and one data transfer operation to be performed. The DSP instruction words include a predefined DSP instruction word having separate source and destination fields for specifying register locations for data sources and data destinations. The RISC instruction words include a predefined RISC instruction word corresponding to the predefined DSP instruction word. The predefined RISC instruction word has separate source and destination fields for specifying register locations for data sources and data destinations. One of the source and destination fields in the predefined RISC instruction word has more bits than the corresponding field in the predefined DSP instruction word.