Toshiharu K Saitoh

US Patent:

6397361, May 28, 2002

Filed:

Apr 2, 1999

Appl. No.:

09/285911

Inventors:

Toshiharu Saitoh - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714724, 714733, 714734, 324 731, 3241581, 324765, 365201, 365218, 36523006

Abstract:

The present invention provides a method and device for reduced-pin integrated circuit I/O testing. In this regard, the present invention provides for the testing of an integrated circuit or chip in a manner which is independent of the number of test pins present on the testing device. The method and device of the present invention are realized through an integrated circuit having two test ports: a scannable I/O test port and a Forcing-Measuring test port, and a plurality of switches. The scannable I/O test port is employed for the input and output of, among other things, scannable shift-register latch data which affects the states of the plurality of switches in the integrated circuit. The Forcing-Measuring test port is employed for, among other things, forcing or measuring voltages and currents associated with the I/O circuits under test through the switches to the circuits under test. The methods of the present invention are embodied in a plurality of test configurations including: an I/O Short-Circuit test configuration which verifies that each I/O is not short-circuited to a supply voltage or to ground; an I/O Negative and Positive Leakage test configuration; a Pull-Up and Pull-Down Resistor test configuration; Differential I/O test configuration; a Package test configuration; an I/O Driver Least Positive Up Level (LPUL) and Most Positive Down Level (MPDL) test configuration; a single-ended I/O receiver LPUL and MPDL test configuration; a differential I/O receiver LPUL and MPDL test configuration; and Differential I/O Terminator Resistor Test configuration.

US Patent:

6819160, Nov 16, 2004

Filed:

Nov 13, 2002

Appl. No.:

10/293340

Inventors:

Toshiharu Saitoh - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01H 3776

US Classification:

327525, 327526, 361104

Abstract:

An apparatus and method for blowing fuses in an integrated circuit. The apparatus and method use a plurality of fuse blowing circuits coupled serially. Each successive fuse blowing circuit is activated by an activate signal generated by a previous fuse blowing circuit. The apparatus and method provide for the fuse blowing operation to be both self-timing and self-testing.

US Patent:

7073100, Jul 4, 2006

Filed:

Nov 11, 2002

Appl. No.:

10/065694

Inventors:

Laura S. Chadwick - Essex Junction VT, US
William R. Corbin - Underhill VT, US
Jeffrey H. Dreibelbis - Williston VT, US
Erik A. Nelson - Waterbury VT, US
Thomas E. Obremski - South Burlington VT, US
Toshiharu Saitoh - South Burlington VT, US
Donald L. Wheater - Hinesburg VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00

US Classification:

714718

Abstract:

A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.

US Patent:

7222274, May 22, 2007

Filed:

Feb 25, 2004

Appl. No.:

10/708342

Inventors:

Michael L. Combs - Essex Junction VT, US
Dale B. Grosch - Burlington VT, US
Toshiharu Saitoh - South Burlington VT, US
Guy M. Vanzo - Westford VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00

US Classification:

714721, 714733, 714710, 365201

Abstract:

A method of testing and repairing an integrated circuit having a total number of fuses for effecting repair of the integrated circuit. The method including: testing a memory array with a set of tests and reserving a first number of the total number of fuses for use in repairing the memory array based on results of the first set of tests; and shmoo testing the memory array by incrementing, decrementing or incrementing and decrementing values of a test parameter until a minimum or maximum value of the test parameter is reached that utilizes a second number of the total number of fuses for use in repairing the memory array to operate at the minimum or maximum value of the test parameter.

US Patent:

7237165, Jun 26, 2007

Filed:

Nov 22, 2004

Appl. No.:

10/994496

Inventors:

Laura S. Chadwick - Essex Junction VT, US
William R. Corbin - Underhill VT, US
Jeffrey H. Dreibelbis - Williston VT, US
Erik A. Nelson - Waterbury VT, US
Thomas E. Obremski - South Burlington VT, US
Toshiharu Saitoh - South Burlington VT, US
Donald L. Wheater - Hinesburg VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G11C 29/00

US Classification:

714733, 714718

Abstract:

A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

US Patent:

7543203, Jun 2, 2009

Filed:

Feb 27, 2004

Appl. No.:

10/708382

Inventors:

Gerry Ashton - Castleton VT, US
Kevin A. Duncan - Milton VT, US
Terry D. Keim - Williston VT, US
Toshiharu Saitoh - South Burlington VT, US
Tad J. Wilder - South Hero VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

A shift register latch (SRL) () compatible with performing level sensitive scan design (LSSD) testing with a single scan clock (SCAN CLK) and single scan clock tree (). The SRL includes a master latch (), a slave latch () and a circuit element () connected between the scan clock tree and the master latch. The scan clock generates a clock signal () having regularly spaced pulses during the scan phase of the LSSD testing. The circuit element generates a short-pulsed signal (′) based on the scan clock signal for triggering the master latch. This short-pulsed signal compensates for any delay in the clock signal due to the physical length of the signal path from the scan clock to the SRL, thereby preventing scanned data from being flushed through a scan chain of the SRLs of the present invention.

US Patent:

63041227, Oct 16, 2001

Filed:

Aug 17, 2000

Appl. No.:

9/641425

Inventors:

Roger P. Gregor - Endicott NY
Steven F. Oakland - Colchester VT
Toshiharu Saitoh - South Burlington VT
Sebastian T. Ventrone - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3289

US Classification:

327202

Abstract:

This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is used instead of two to provide lower power, and less switching devices in clocks splitters are used, which also provides lower power. Additionally, a flushable single clock splitter is provided that allows one clock tree to be used up to the flushable single clock splitter and provides two clocks on the output of the flushable single clock splitter. This saves some power yet still allows for dual clock flip flop designs.

US Patent:

56895143, Nov 18, 1997

Filed:

Sep 30, 1996

Appl. No.:

8/724573

Inventors:

Toshiharu Saitoh - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

371 212

Abstract:

A method and apparatus for testing or verifying proper operation of an address system of a memory system are provided. The address system includes a write unit for driving write word lines, based on a write address, and a read unit for driving read word lines, based on a read address. A common address is applied to the write unit and read unit, and the outputs thereof are compared for equivalency, using a verification circuit. Proper operation of the address system is indicated by the verification circuit if the outputs of the write and read units are equivalent, and improper operation is indicated if the outputs are not equivalent.