Tri Thai Hoang

US Patent:

8411490, Apr 2, 2013

Filed:

Jul 10, 2004

Appl. No.:

10/890430

Inventors:

David C. Lawson - Haymarket VA, US
Edward Maher - Manassas VA, US
Shankarnarayana Ramaswamy - Chantilly VA, US
Tri Minh Hoang - Clifton VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G11C 11/00

US Classification:

365154

Abstract:

A sense amplifier for static random access memories is disclosed. The sense amplifier includes a pair of inverters cross-coupled to each other. The sense amplifier also includes means for equalizing the charges within the pair of inverters before performing a sense operation, and means for sensing a current difference between a bitline and its complement from a memory cell during the sense operation.

US Patent:

62156942, Apr 10, 2001

Filed:

Apr 20, 2000

Appl. No.:

9/553595

Inventors:

Bin Li - Fairfax VA
Livia L. Zien - Fredericksburg VA
David C. Lawson - Fredericksburg VA
Tatia B. Butts - Manassas VA
Tri M. Hoang - Clifton VA

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G11C 1100

US Classification:

365156

Abstract:

A single event upset hardened multiport memory cell to be utilized in a register file is disclosed. The single event upset hardened multiport memory cell includes a storage cell, a write bitline, a read bitline. The storage cell, which is utilized for storing data, includes first and second sets of cross-coupled transistors and first and second sets of isolation transistors. The first and second sets of isolation transistors are respectively coupled to the first and second set of cross-coupled transistors such that two inversion paths are formed between the two sets of cross-coupled transistors and the two sets of isolation transistors. Coupled to the storage cell, the write bitline inputs write data to the storage cell. Also coupled to the storage cell, the read bitline outputs read data from the storage cell.

US Patent:

61697028, Jan 2, 2001

Filed:

May 26, 1999

Appl. No.:

9/320207

Inventors:

Tri Minh Hoang - Clifton VA
Livia Zien - Manassas VA
Scott Doyle - Centreville VA
David Lawson - Harwood VA

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G11C 800

US Classification:

36523006

Abstract:

A memory device includes a plurality of address on-chip receivers (OCRs), an address decoder coupled to the address OCRs, a plurality of first delay circuits coupled between the address OCRs and the address decoder, and a plurality of chip select bypass circuits. Each chip select bypass circuit is respectively coupled to one of the plurality of first delay circuits for initially reducing a delay therein responsive to a control signal. The chip select bypass circuit includes a second delay circuit having a delay less than the first delay circuit, and a disable circuit. The disable circuit disables the first delay circuit and selectively couples the second delay circuit in place of the first delay circuit responsive to the control signal.

US Patent:

61816418, Jan 30, 2001

Filed:

May 26, 1999

Appl. No.:

9/320227

Inventors:

Dongho Lee - Manassas VA
Tri Minh Hoang - Clifton VA
Livia Zien - Manassas VA
Scott Doyle - Centreville VA
David Lawson - Harwood VA

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G11C 800

US Classification:

3652335

Abstract:

A memory device includes a plurality of memory cells arranged in rows and columns. The memory cells are divided into a plurality of sub-arrays. The memory cell further includes a plurality of word lines connecting rows of the memory cells, and a plurality of bit line pairs connecting columns of the memory cells. An address transition detect (ATD) circuit detects an address transition for a selected memory cell and generates an ATD pulse in response thereto. A respective bit line precharge circuit is associated with each of the plurality of sub-arrays. An ATD pulse distribution circuit distributes the ATD pulse to only a selected sub-array containing the selected memory cell to activate only the bit line precharge circuit of the selected sub-array and not activate precharge circuits of other non-selected sub-arrays.