Tri Minh Vo

US Patent:

8534516, Sep 17, 2013

Filed:

Nov 17, 2010

Appl. No.:

12/948441

Inventors:

Tri D. Vo - San Diego CA, US

International Classification:

B60R 9/12

US Classification:

224318, 224324, 224329

Abstract:

The present invention includes a polyurethane foam block placed on a vehicle rooftop to protect the vehicle's rooftop from damage during transport of cargo supported thereon, further comprising a generally trapezoidal shape of a length substantially equal than a width of the vehicle, further having a pair of opposing flexible extending ear portions. The bottom surface comprises a corrugated base of foam material to conform to the curvature of the vehicle's rooftop. An elastic fabric covers the device and the ear portions and further comprises a means for receiving rigging material in securing the device to the existing vehicle rooftop and preventing unwanted cargo shifting.

US Patent:

49282905, May 22, 1990

Filed:

Nov 7, 1988

Appl. No.:

7/268147

Inventors:

Tri T. Vo - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

H04L 702

US Classification:

375118

Abstract:

A circuit for the stable synchronization of an asynchronous data signal. The circuit comprises a first latch for receiving a first asynchronous data signal, a first delayed system clock signal, and a synchronized reset signal and for providing a system clock synchronized version of the first asynchronous data signal. A first delaying circuit receives a system clock signal and the first asynchronous data signal and provides the first delayed system clock signal. The circuit also includes a second latch for receiving a second asynchronous data signal which is a function of the inverse of the first asynchronous data signal and a second delayed system clock signal, and for providing the synchronized reset signal. A second delaying circuit receives the system clock signal and the first asynchronous data signal and provide the second delayed system clock signal.

US Patent:

57129860, Jan 27, 1998

Filed:

Dec 19, 1995

Appl. No.:

8/580000

Inventors:

Tri Tinh Vo - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1300

US Classification:

395309

Abstract:

A method and apparatus of bridging a first device with a second device operating at a different clock frequency is described. The apparatus comprises a first bus slave interface coupled to the first device, and a second bus master interface coupled to the first bus slave interface and the second device, a second bus slave interface coupled to the second device, and a first bus master interface coupled to the second bus slave interface and the first device.

US Patent:

46943951, Sep 15, 1987

Filed:

Nov 25, 1985

Appl. No.:

6/801361

Inventors:

Rocky M. Young - Escondido CA
Tri T. Vo - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1210

US Classification:

364200

Abstract:

A system is disclosed which reduces the cycle time required for performing virtual look-ahead memory operations in computer systems employing random access memory and paging. In a preferred embodiment of the invention, a processor (CPU) outputs a desired virtual address to an address translation unit (ATU) and to a memory output control unit (MOC) and also outputs processor signals to the ATU and to a memory state generator (MSG). The virtual address is comprised of a first real address and a second virtual address. During a first cycle this first real address is gated through a memory output control unit (MOC) to cause an addressable memory, which is arranged to store data in a page format, to commence memory addressing prior to the completion of translation by the ATU. During the first cycle the ATU translates the second virtual address into second and third real address portions. During a second cycle a decoder decodes the third real address portion to develop memory operation signals which determine which one of a plurality of virtual memory operations is to be performed.

US Patent:

51685612, Dec 1, 1992

Filed:

Feb 16, 1990

Appl. No.:

7/481098

Inventors:

Tri T. Vo - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1204

US Classification:

395425

Abstract:

Apparatus for correcting the byte alignment of multiple-byte data words during DMA word transfers. The apparatus includes a four-byte input word bus and a four-byte output word bus. A carrier register stores the second, third and fourth bytes of a first four-byte data word received on the input bus. A data selector including four 4:1 multiplexers determines which of the three stored word bytes and which of four bytes corresponding to a second data word received on the input bus should be placed on the four-byte output word bus and the sequential order of the bytes on the bus.