Trinh T Van

US Patent:

7544398, Jun 9, 2009

Filed:

Apr 26, 2006

Appl. No.:

11/411425

Inventors:

Jane P. Chang - Los Angeles CA, US
Trinh Tu Van - Portland OR, US
Tony Chiang - Campbell CA, US
Chandra Deshpandey - Fremont CA, US
Karl Lesser - San Jose CA, US

Assignee:

The Regents of the Univesity of California - Los Angeles CA

International Classification:

H05H 1/24

US Classification:

427537, 437539, 117 84, 117108

Abstract:

The invention relates to methods for producing doped thin layers on substrates comprising the steps of depositing a dopant precursor on the substrate via an atomic layer deposition technique; and exposing the deposited dopant precursor to radicals. The methods can further comprise depositing a compound adjacent the dopant metal via an atomic layer deposition technique; and exposing the deposited compound to radicals, thereby providing a host. The invention relates to articles comprising approximately atomically thin layers of metals or metal oxides doped with at least one different metal or metal oxide. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present invention.

US Patent:

20200203602, Jun 25, 2020

Filed:

Sep 28, 2017

Appl. No.:

16/641582

Inventors:

- Santa Clara CA, US
Oleg Golonzka - Beaverton OR, US
Nathan Strutt - Beaverton OR, US
Patrick J. Hentges - Portland OR, US
Trinh T. Van - Hillsboro OR, US
Hiten Kothari - Beaverton OR, US
Ameya S. Chaudhari - Hillsboro OR, US
Matthew J. Andrus - Hillsboro OR, US
Timothy E. Glassman - Portland OR, US
Dragos Seghete - Portland OR, US
Christopher J. Wiegand - Portland OR, US
Daniel G. Ouellette - Portland OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 45/00
H01L 23/528
H01L 27/24

Abstract:

An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.