Trinh T Van

US Patent:

20200203602, Jun 25, 2020

Filed:

Sep 28, 2017

Appl. No.:

16/641582

Inventors:

- Santa Clara CA, US
Oleg Golonzka - Beaverton OR, US
Nathan Strutt - Beaverton OR, US
Patrick J. Hentges - Portland OR, US
Trinh T. Van - Hillsboro OR, US
Hiten Kothari - Beaverton OR, US
Ameya S. Chaudhari - Hillsboro OR, US
Matthew J. Andrus - Hillsboro OR, US
Timothy E. Glassman - Portland OR, US
Dragos Seghete - Portland OR, US
Christopher J. Wiegand - Portland OR, US
Daniel G. Ouellette - Portland OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 45/00
H01L 23/528
H01L 27/24

Abstract:

An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.