Tuan Quoc Vo

Address:

13101 Yockey St APT 138, Garden Grove, CA 92844

Phone:

7144686771

VIN:

5J6RM3H72CL046408

Make:

HONDA

Model:

CR-V

Year:

2012

Address:

10550 Greenwood Rd, Glen Allen, VA 23059

VIN:

5TDZK23C97S038868

Make:

TOYOTA

Model:

SIENNA

Year:

2007

US Patent:

6416158, Jul 9, 2002

Filed:

Sep 29, 1999

Appl. No.:

09/407908

Inventors:

Philip D. Floyd - Sunnyvale CA
Tuan Anh Vo - Hawthorne CA
Kaiser H. Wong - Torrance CA
Gregory B. Anderson - Woodside CA
Eric Peeters - Fremont CA
Jaan Noolandi - Mississauga, CA
Meng H. Lean - Briarcliff Manor NY
Armin R. Volkel - Mississauga, CA
John E. Northrup - Palo Alto CA
Jurgen Daniel - Mountain View CA
G. A. Neville Connell - Alpine CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

B41J 2035

US Classification:

347 21

Abstract:

A device for the transport and/or metering of marking material includes a plurality of phased electrodes, for example formed on a substrate. An electrostatic traveling wave may be generated along the electrodes to sequentially attract particles of marking material, and thereby transport them to a desired location. The electrodes may be formed in a planar structure. A matrix interconnection scheme allows for reduced lead count.

US Patent:

20110151963, Jun 23, 2011

Filed:

Dec 22, 2009

Appl. No.:

12/644325

Inventors:

Felix Roderick Zafra Doctor - Phillips Ranch CA, US
Tuan Anh Vo - San Dimas CA, US

International Classification:

A63F 9/24

US Classification:

463 25, 463 30, 463 42, 463 43

Abstract:

A gaming device for taking sports related bets wherein the house offers various sports games for betting, based upon the final score combination, allowing players to select desired game(s) to place bet by picking the slot(s) on the 10×10 matrix. At end of the selected sports game, a winning slot will be determined from the slots picked before the cut-off time. Spectators of such sports will get a higher sense of thrill and better sense of satisfaction along with the betting device and the method disclosed herein.

US Patent:

20120236378, Sep 20, 2012

Filed:

Sep 16, 2011

Appl. No.:

13/235188

Inventors:

Adrian Stoica - Altadena CA, US
David Zhu - North Hills CA, US
Mohammad Mehdi Mojarradi - La Canada CA, US
Tuan A. Vo - Hawthorne CA, US

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

G02F 3/00
H03K 19/20

US Classification:

359108, 326104

Abstract:

Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

US Patent:

62910884, Sep 18, 2001

Filed:

Sep 30, 1998

Appl. No.:

9/163518

Inventors:

Kaiser H. Wong - Torrance CA
Tuan Anh Vo - Hawthorne CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

B32B 700

US Classification:

428698

Abstract:

An inorganic, top-surface, semiconducting dielectric overcoat, having a selected time constant permits electric field charge and dissipation at a selected rate to facilitate particulate material movement over an underlying electrode grid. The coating may be made from nitrides, oxides or oxy-nitrides of silicon, or amorphous silicon. A planarized, wear resistant, chemically stable surface, and minimized inter-electrode build-up are also provided by the overcoat.

US Patent:

53828267, Jan 17, 1995

Filed:

Dec 21, 1993

Appl. No.:

8/170848

Inventors:

Mohamad M. Mojaradi - Los Angeles CA
Tuan A. Vo - Hawthorne CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H01L 2358
H01L 2976
H03K 17687

US Classification:

257489

Abstract:

A high current, high voltage transistor which can be easily electrically stacked to extend the voltage range and uses less silicon area than a conventional stacked transistor configuration and a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values. Also, a star shaped field plate design which provides the greatest breakdown voltages with the highest ohmic values. The field plate is constructed using several concentric rings connected by fingers that are wider at towards the center of the concentric rings and narrower towards the perimeter of the concentric rings.

US Patent:

53492234, Sep 20, 1994

Filed:

Dec 14, 1993

Appl. No.:

8/166400

Inventors:

Mohamad M. Mojaradi - Los Angeles CA
Tuan A. Vo - Hawthorne CA
Steven A. Buhler - Redondo Beach CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H01L 2968
H01L 2978
H01L 2940

US Classification:

257329

Abstract:

A vertical transistor which is built in a substrate of a given first carrier type utilizing standard processes but which has a unique layout which facilitates high voltage, high current operation while still conserving space. The transistor is built utilizing a repeatable combination gate/source area that is built in the upper area of the substrate such that the remaining lower portion of the substrate underneath the combination gate/source area is the drain area of the transistor.

US Patent:

54242266, Jun 13, 1995

Filed:

Apr 11, 1994

Appl. No.:

8/225673

Inventors:

Tuan A. Vo - Hawthorne CA
Mohamad M. Mojaradi - Los Angeles CA
Guillermo Lao - Hawthorne CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H01L 21266
H01L 21336
H01L 218238
H01L 218236

US Classification:

437 30

Abstract:

A FET which can be formed on a silicon substrate and which can operate in the enhancement mode. The n+ source and drain are centrally located within n-wells which extend under the gate area, and are separated by a distance. By appropriately choosing the distance between n-wells, different threshold voltages can be obtained for several transistors on the same chip.

US Patent:

57179867, Feb 10, 1998

Filed:

Jun 24, 1996

Appl. No.:

8/668759

Inventors:

Tuan Anh Vo - Hawthorne CA
Mohammad M. Mojarradi - Pullman WA
Dennis W. Sandstrom - Sylmar CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G03G 1506

US Classification:

399291

Abstract:

A development system which includes a flexible donor belt having groups of electrode array near the surface of the belt is disclosed. The Electrode array has group areas in which perform the function of: Loading; Transferring; Developing; Transferring and Unloading. Each electrode array group area is independently addressable and operatively connected to voltage source in order to supply a voltage in the order of. quadrature. 0-1000 volts AC or DC to each group area. The electrodes array group area picks up the toner from the magnetic brush. An electrode array group area connected to the voltage source via phase shifting circuitry such that a traveling wave pattern is established. The electrostatic field forming the traveling wave pattern pushes the charged toner particles about the surface of the donor belt from the magnetic brush to the photoconductive belt where they are transferred to the latent electrostatic images on the belt by an electrode group area which generates a toner cloud in the development zone. Thereafter, toner is moved by an electrode array group area where an electrode group area is bias to unload remaining toner off the belt.