Tyler G Johnson

US Patent:

6928629, Aug 9, 2005

Filed:

Jun 3, 2003

Appl. No.:

10/453720

Inventors:

Tyler James Johnson - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 4, 716 1, 716 5, 716 6, 714 25

Abstract:

In one embodiment, the invention is directed to a method of processing a database comprising information regarding hardware design language (“HDL”) events occurring during a simulation of a hardware design. The method comprises identifying in the database all HDL events comprising observability events; obtaining from each of the identified observability HDL events information pertaining to a signal driving the identified observability HDL event observed on an observability bus; and creating a data structure comprising a plurality of entries, wherein each of the entries corresponds to one of the signals observed on the observability bus and contains signal information pertaining to the one of the observed signals.

US Patent:

6949956, Sep 27, 2005

Filed:

Jun 3, 2003

Appl. No.:

10/453129

Inventors:

Tyler James Johnson - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H03K019/00

US Classification:

326 99, 327276, 327277, 327284

Abstract:

A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.

US Patent:

7107394, Sep 12, 2006

Filed:

Mar 28, 2003

Appl. No.:

10/402628

Inventors:

Tyler James Johnson - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 8/04

US Classification:

711110

Abstract:

In one embodiment, an apparatus is disclosed for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; and logic for comparing a value of the counter with a preselected register address on each count of the counter, wherein the logic for comparing comprises a comparator having an input connected to receive the preselected register address, an input connected to receive the value of the counter, and an output operable to drive a select signal of a multiplexer provided for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address.

US Patent:

7146538, Dec 5, 2006

Filed:

Mar 28, 2003

Appl. No.:

10/402092

Inventors:

Tyler James Johnson - Plano TX, US
Theodore Carter Briggs - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 30, 714 27, 714726, 714727, 326 16

Abstract:

A bus interface module (“BIM”) connectable to a debug bus is described. In one embodiment, the BIM comprises a plurality of BIM segments connected in a ring such that an output of each BIM is connected to an input of a next BIM via the debug bus, the BIM comprising logic for receiving data from a previous BIM, logic for receiving data from local logic associated with the BIM, and logic for combining the previous BIM data with local logic data and transmitting the combined data to a next BIM.

US Patent:

7188277, Mar 6, 2007

Filed:

Mar 28, 2003

Appl. No.:

10/402034

Inventors:

Tyler James Johnson - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 30, 714726, 714727

Abstract:

An integrated circuit (“IC”) comprising a plurality of logic modules. The IC further comprises a plurality of bus segments each associated with one of the logic modules; a debug bus interconnecting the bus segments in a ring; and a debug port connected to the debug bus for accessing debug data on the debug bus. Each bus segment takes in data from the logic module associated therewith and outputs the data to the debug bus to be forwarded to the next bus segment along the ring.

US Patent:

7200778, Apr 3, 2007

Filed:

Mar 28, 2003

Appl. No.:

10/402122

Inventors:

Tyler James Johnson - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 47, 702 58, 702 59

Abstract:

In one embodiment, the invention is directed to a method of verifying conditions occurring during a simulation of a hardware design. The method comprises logging each occurrence of at least one specified condition in a first log; logging signals observed at an observability port in a second log; and comparing the first and second logs to determine whether for each occurrence of the at least one specified condition logged in the first log, a corresponding entry identifying a signal expected to be observed responsive to occurrence of the at least one specified condition is logged in the second log.

US Patent:

7225394, May 29, 2007

Filed:

May 8, 2003

Appl. No.:

10/431941

Inventors:

Tyler James Johnson - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/08
G06F 7/02

US Classification:

714797, 714819

Abstract:

A circuit for correcting errors in an N times duplicated signal is described. The circuit comprises a plurality of AND gates, wherein each of the AND gates comprises a plurality of inputs for receiving a copy of the N times duplicated signal; and an OR gate having a plurality of inputs, wherein each input of the OR gate is connected to an output of one of the AND gates, wherein an output of the OR gate comprises the corrected signal.

US Patent:

7228472, Jun 5, 2007

Filed:

Jan 11, 2005

Appl. No.:

11/032928

Inventors:

Tyler J. Johnson - Murphy TX, US
Ryan Lee Akkerman - Allen TX, US
John A. Benavides - Garland TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01R 31/28
G06F 12/00

US Classification:

714724, 711100

Abstract:

One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a control signal. A control system provides the control signal based on a number of store cycles relative to an event to define the set of data, the number of store cycles varying based on the store signal.